Daniel Henrique Barboza ce7fb32827 hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx() ...

We're hardcoding faulting type as READ, where it could very well be a
write access, and we're not recording the faulting addr/iova.

A note was added in the fault_type logic because I wasn't able to
trivially handle a probable code repeitition it in this same patch.
Something to do in a later date.

Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3564
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260701092241.307801-1-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2026-07-09 15:35:24 +10:00

..

aia.c

hw/riscv/aia: Configure stride for the M-mode IMSIC

2026-07-01 19:59:10 +10:00

aia.h

hw/riscv/aia: Configure stride for the M-mode IMSIC

2026-07-01 19:59:10 +10:00

boot.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

boston-aia.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

cps.c

hw/riscv: Add support for RISCV CPS

2026-01-09 15:13:20 +10:00

fdt-common.c

hw/riscv, target/riscv: move pmu fdt function to fdt-common.c

2026-07-09 14:58:02 +10:00

k230.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

Kconfig

hw/riscv/atlantis: Add some i2c peripherals

2026-07-01 19:59:10 +10:00

meson.build

hw/riscv: Add Tenstorrent Atlantis machine

2026-07-01 19:59:10 +10:00

microblaze-v-generic.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

microchip_pfsoc.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

numa.c

hw/riscv/numa: make numa_enabled() public

2026-06-16 20:01:11 +10:00

opentitan.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

riscv_hart.c

hw/riscv/riscv_hart.c isolate tcg only bits

2026-07-09 14:58:03 +10:00

riscv-iommu-bits.h

hw/riscv/riscv-iommu: forbid GATE/SADE if caps.AMO_HWADD is zero

2026-07-09 15:33:37 +10:00

riscv-iommu-hpm.c

hw/riscv/riscv-iommu: rename regs_rw to regs

2026-07-01 19:59:09 +10:00

riscv-iommu-hpm.h

hw/riscv/riscv-iommu: add hpm events mmio write

2025-03-04 15:42:54 +10:00

riscv-iommu-pci.c

hw/riscv: Set IOMMU PAS via property

2026-02-25 23:46:04 +01:00

riscv-iommu-sys.c

hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write

2026-07-09 14:58:02 +10:00

riscv-iommu.c

hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx()

2026-07-09 15:35:24 +10:00

riscv-iommu.h

hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write

2026-07-09 14:58:02 +10:00

shakti_c.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

sifive_e.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

sifive_u.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

spike.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

trace-events

hw/riscv: add IOMMU HPM trace events

2025-03-04 15:42:54 +10:00

trace.h

hw/riscv: add RISC-V IOMMU base emulation

2024-10-31 13:51:24 +10:00

tt_atlantis.c

hw/riscv, target/riscv: move pmu fdt function to fdt-common.c

2026-07-09 14:58:02 +10:00

virt-acpi-build.c

hw/riscv/aia: Provide number of irq sources

2026-07-01 19:59:10 +10:00

virt.c

hw/riscv, target/riscv: move pmu fdt function to fdt-common.c

2026-07-09 14:58:02 +10:00

xiangshan_kmh.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00