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hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write

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The riscv-iommu spec requires that the IOMMU records its own generated
MSI write faults.

Fixes: 01c1caa9d1 ("hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3572
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Message-ID: <20260629165954.1018123-1-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
2026-06-29 13:59:54 -03:00
committed by Alistair Francis
parent 11486349ad
commit 58e801f74e
3 changed files with 17 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
hw/riscv/riscv-iommu-sys.c
View File

@@ -26,6 +26,7 @@
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qom/object.h"
#include "target/riscv/cpu_bits.h"
#include "trace.h"
#include "riscv-iommu.h"
@@ -143,7 +144,20 @@ static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
address_space_stl_le(&address_space_memory, msi_addr,
msi_data, MEMTXATTRS_UNSPECIFIED, &result);
trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
if (result == MEMTX_OK) {
trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
} else {
/* Record an access fault error in the fault queue */
struct riscv_iommu_fq_record ev = { 0 };
RISCVIOMMUState *iommu = &s->iommu;
ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_CAUSE,
RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT);
ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_TTYPE,
RISCV_IOMMU_FQ_TTYPE_UADDR_WR);
riscv_iommu_fault(iommu, &ev);
}
}
static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,

3
hw/riscv/riscv-iommu.c
View File

@@ -118,8 +118,7 @@ void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type)
}
}
static void riscv_iommu_fault(RISCVIOMMUState *s,
struct riscv_iommu_fq_record *ev)
void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *ev)
{
uint32_t ctrl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQCSR);
uint32_t head = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQH) & s->fq_mask;

1
hw/riscv/riscv-iommu.h
View File

@@ -103,6 +103,7 @@ void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
void riscv_iommu_reset(RISCVIOMMUState *s);
void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type);
void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *ev);
typedef struct RISCVIOMMUContext RISCVIOMMUContext;
/* Device translation context state. */