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hw/riscv/riscv-iommu.c: check reserved MSI PTE basic bits

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We need to throw an MSI_MISCONFIGURED error when any of the reserved PTE
bits (first doubleword only) are set.

Fixes: Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3563
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Message-ID: <20260629125719.679626-1-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
2026-06-29 09:57:19 -03:00
committed by Alistair Francis
parent 9158c900ab
commit 11486349ad
1 changed files with 21 additions and 0 deletions
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21
hw/riscv/riscv-iommu.c
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@@ -677,6 +677,27 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
switch (get_field(pte[0], RISCV_IOMMU_MSI_PTE_M)) {
case RISCV_IOMMU_MSI_PTE_M_BASIC:
/*
* riscv-iommu spec MSI PTE basic translate mode:
* "When an MSI PTE has fields V = 1, C = 0, and M = 3
* (basic translate mode), the PTE's complete format is:
* First doubleword: bit 63 C, = 0
* bits 53:10 PPN
* bits 2:1 M, = 3
* bit 0 V, = 1
* All other bits of the first doubleword are reserved
* and must be set to zeros by software. The second
* doubleword is ignored by an IOMMU so is free for
* software to use."
*
* In other words, bits 62:54 and 9:3 of pte[0] are reserved.
*/
if (pte[0] & (GENMASK_ULL(62, 54) | GENMASK_ULL(9, 3))) {
res = MEMTX_DECODE_ERROR;
cause = RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED;
goto err;
}
/* MSI Pass-through mode */
addr = PPN_PHYS(get_field(pte[0], RISCV_IOMMU_MSI_PTE_PPN));