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hw/riscv/riscv-iommu: rename regs_rw to regs

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The existing nomenclature can be misleading: regs_rw can cosplay as
'read and write' mask, in particular because we have regs_ro which is a
read only mask.

regs_rw is the current reg value, and all bits that aren't on the
regs_ro mask is considered r/w bits.

Rename regs_rw to 'regs' to be on par with the nomenclature other
devices uses (e.g. cadence_gem).

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260625210833.3294437-2-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
2026-06-25 18:08:32 -03:00
committed by Alistair Francis
parent b3b4a424e2
commit 8a34849f5b
3 changed files with 35 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/riscv/riscv-iommu-hpm.c
View File

@@ -60,8 +60,8 @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)
const uint32_t off = ctr_idx << 3;
uint64_t cntr_val;
cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
cntr_val = ldq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
stq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
trace_riscv_iommu_hpm_incr_ctr(cntr_val);

36
hw/riscv/riscv-iommu.c
View File

@@ -2034,8 +2034,8 @@ static void riscv_iommu_process_cq_control(RISCVIOMMUState *s)
s->cq_mask = (2ULL << get_field(base, RISCV_IOMMU_CQB_LOG2SZ)) - 1;
s->cq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_CQB_PPN));
stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~s->cq_mask);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQH], 0);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQT], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_CQH], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_CQT], 0);
ctrl_set = RISCV_IOMMU_CQCSR_CQON;
ctrl_clr = RISCV_IOMMU_CQCSR_BUSY | RISCV_IOMMU_CQCSR_CQMF |
RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CMD_TO |
@@ -2075,8 +2075,8 @@ static void riscv_iommu_process_fq_control(RISCVIOMMUState *s)
s->fq_mask = (2ULL << get_field(base, RISCV_IOMMU_FQB_LOG2SZ)) - 1;
s->fq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_FQB_PPN));
stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQH], 0);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQT], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_FQH], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_FQT], 0);
ctrl_set = RISCV_IOMMU_FQCSR_FQON;
ctrl_clr = RISCV_IOMMU_FQCSR_BUSY | RISCV_IOMMU_FQCSR_FQMF |
RISCV_IOMMU_FQCSR_FQOF;
@@ -2105,8 +2105,8 @@ static void riscv_iommu_process_pq_control(RISCVIOMMUState *s)
s->pq_mask = (2ULL << get_field(base, RISCV_IOMMU_PQB_LOG2SZ)) - 1;
s->pq_addr = PPN_PHYS(get_field(base, RISCV_IOMMU_PQB_PPN));
stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQH], ~s->pq_mask);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQH], 0);
stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQT], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_PQH], 0);
stl_le_p(&s->regs[RISCV_IOMMU_REG_PQT], 0);
ctrl_set = RISCV_IOMMU_PQCSR_PQON;
ctrl_clr = RISCV_IOMMU_PQCSR_BUSY | RISCV_IOMMU_PQCSR_PQMF |
RISCV_IOMMU_PQCSR_PQOF;
@@ -2276,9 +2276,9 @@ static void riscv_iommu_write_reg_val(RISCVIOMMUState *s,
{
uint64_t ro = ldn_le_p(&s->regs_ro[reg_addr], size);
uint64_t wc = ldn_le_p(&s->regs_wc[reg_addr], size);
uint64_t rw = ldn_le_p(&s->regs_rw[reg_addr], size);
uint64_t curr_val = ldn_le_p(&s->regs[reg_addr], size);
stn_le_p(dest, size, ((rw & ro) | (data & ~ro)) & ~(data & wc));
stn_le_p(dest, size, ((curr_val & ro) | (data & ~ro)) & ~(data & wc));
}
static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
@@ -2378,12 +2378,12 @@ static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr,
* is set IOMMU behavior of additional writes to the register
* is UNSPECIFIED.
*/
riscv_iommu_write_reg_val(s, &s->regs_rw[addr], addr, size, data);
riscv_iommu_write_reg_val(s, &s->regs[addr], addr, size, data);
/* Busy flag update, MSB 4-byte register. */
if (busy) {
uint32_t rw = ldl_le_p(&s->regs_rw[regb]);
stl_le_p(&s->regs_rw[regb], rw | busy);
uint32_t rw = ldl_le_p(&s->regs[regb]);
stl_le_p(&s->regs[regb], rw | busy);
}
/* Process HPM writes and update any internal state if needed. */
@@ -2428,13 +2428,13 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
* it's not dependent over the timer callback and is computed
* from cycle overflow.
*/
val = ldq_le_p(&s->regs_rw[addr]);
val = ldq_le_p(&s->regs[addr]);
val |= (riscv_iommu_hpmcycle_read(s) & RISCV_IOMMU_IOHPMCYCLES_OVF)
? RISCV_IOMMU_IOCOUNTOVF_CY
: 0;
ptr = (uint8_t *)&val + (addr & 3);
} else {
ptr = &s->regs_rw[addr];
ptr = &s->regs[addr];
}
val = ldn_le_p(ptr, size);
@@ -2529,7 +2529,7 @@ static void riscv_iommu_instance_init(Object *obj)
s->cap |= RISCV_IOMMU_CAP_PD8;
/* register storage */
s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
@@ -2554,7 +2554,7 @@ static void riscv_iommu_instance_finalize(Object *obj)
{
RISCVIOMMUState *s = RISCV_IOMMU(obj);
g_free(s->regs_rw);
g_free(s->regs);
g_free(s->regs_ro);
g_free(s->regs_wc);
@@ -2608,8 +2608,8 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
"riscv-iommu-regs", RISCV_IOMMU_REG_SIZE);
/* Set power-on register state */
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_CAP], s->cap);
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_FCTL], 0);
stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap);
stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0);
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL],
~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI));
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP],
@@ -2634,7 +2634,7 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
RISCV_IOMMU_PQCSR_BUSY);
stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_IPSR], ~0);
stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_ICVEC], 0);
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_DDTP], s->ddtp);
stq_le_p(&s->regs[RISCV_IOMMU_REG_DDTP], s->ddtp);
/* If debug registers enabled. */
if (s->cap & RISCV_IOMMU_CAP_DBG) {
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_TR_REQ_IOVA], 0);

26
hw/riscv/riscv-iommu.h
View File

@@ -76,9 +76,13 @@ struct RISCVIOMMUState {
/* MMIO Hardware Interface */
MemoryRegion regs_mr;
uint8_t *regs_rw; /* register state (user write) */
uint8_t *regs; /* current register state */
uint8_t *regs_wc; /* write-1-to-clear mask */
uint8_t *regs_ro; /* read-only mask */
/*
* read-only mask. NOTE: bits not present in this RO
* mask are assumed to be read and write.
*/
uint8_t *regs_ro;
QLIST_ENTRY(RISCVIOMMUState) iommus;
QLIST_HEAD(, RISCVIOMMUSpace) spaces;
@@ -120,39 +124,39 @@ struct RISCVIOMMUContext {
static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s,
unsigned idx, uint32_t set, uint32_t clr)
{
uint32_t val = ldl_le_p(s->regs_rw + idx);
stl_le_p(s->regs_rw + idx, (val & ~clr) | set);
uint32_t val = ldl_le_p(s->regs + idx);
stl_le_p(s->regs + idx, (val & ~clr) | set);
return val;
}
static inline void riscv_iommu_reg_set32(RISCVIOMMUState *s, unsigned idx,
uint32_t set)
{
stl_le_p(s->regs_rw + idx, set);
stl_le_p(s->regs + idx, set);
}
static inline uint32_t riscv_iommu_reg_get32(RISCVIOMMUState *s, unsigned idx)
{
return ldl_le_p(s->regs_rw + idx);
return ldl_le_p(s->regs + idx);
}
static inline uint64_t riscv_iommu_reg_mod64(RISCVIOMMUState *s, unsigned idx,
uint64_t set, uint64_t clr)
{
uint64_t val = ldq_le_p(s->regs_rw + idx);
stq_le_p(s->regs_rw + idx, (val & ~clr) | set);
uint64_t val = ldq_le_p(s->regs + idx);
stq_le_p(s->regs + idx, (val & ~clr) | set);
return val;
}
static inline void riscv_iommu_reg_set64(RISCVIOMMUState *s, unsigned idx,
uint64_t set)
{
stq_le_p(s->regs_rw + idx, set);
stq_le_p(s->regs + idx, set);
}
static inline uint64_t riscv_iommu_reg_get64(RISCVIOMMUState *s,
unsigned idx)
unsigned idx)
{
return ldq_le_p(s->regs_rw + idx);
return ldq_le_p(s->regs + idx);
}
#endif