Wang Yechao 83a87a38b6 target/riscv/kvm: add extensions after v7.1-rc4 update ...

Expose zilsd, zclsd and zalasr.

Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260707072610.403595-1-wang.yechao255@zte.com.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2026-07-09 15:38:59 +10:00

..

kvm

target/riscv/kvm: add extensions after v7.1-rc4 update

2026-07-09 15:38:59 +10:00

tcg

target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic

2026-07-09 14:58:03 +10:00

arch_dump.c

…

common-semi-target.c

include/semihosting/common-semi: extract common_semi API

2025-09-26 09:55:19 +01:00

cpu_bits.h

target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks

2026-05-27 11:50:12 +02:00

cpu_cfg_fields.h.inc

target/riscv: Add big-endian CPU configuration field and reset logic

2026-06-16 13:50:25 +10:00

cpu_cfg.h

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

cpu_user.h

…

cpu_vendorid.h

target/riscv: tt-ascalon: Add Tenstorrent mvendorid

2026-04-29 13:38:13 +10:00

cpu-param.h

exec: Drop TARGET_PHYS_ADDR_SPACE_BITS

2026-02-25 23:46:04 +01:00

cpu-qom.h

target/riscv: add thead-c908 cpu support

2026-06-16 20:01:11 +10:00

cpu.c

target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()

2026-07-09 14:58:03 +10:00

cpu.h

target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic

2026-07-09 14:58:03 +10:00

gdbstub.c

target/riscv/gdbstub.c: isolate TCG only checks

2026-07-09 14:58:03 +10:00

helper.h

target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f

2026-05-22 09:45:46 +10:00

insn16.decode

target/riscv: Add Zilsd and Zclsd extension support

2026-01-09 15:01:10 +10:00

insn32.decode

disas/riscv.c: add 'cbo' insns to disassembler

2026-06-15 13:10:14 +10:00

instmap.h

…

internals.h

target/riscv: Implement runtime data endianness via MSTATUS bits

2026-06-16 13:40:38 +10:00

Kconfig

…

machine.c

target/riscv: move debug.h to tcg subdir

2026-07-09 14:58:03 +10:00

meson.build

target/riscv: move pmp files to tcg subdir

2026-07-09 14:58:03 +10:00

monitor.c

target/riscv: move csr.h to tcg subdir

2026-07-09 14:58:03 +10:00

riscv-qmp-cmds.c

target/riscv: move csr.h to tcg subdir

2026-07-09 14:58:03 +10:00

sbi_ecall_interface.h

…

time_helper.c

target/riscv: gate riscv_cpu_update_mip with tcg_enabled()

2026-07-09 14:58:03 +10:00

time_helper.h

target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

2025-07-04 21:09:48 +10:00

trace-events

target/riscv: add trace in riscv_raise_exception()

2025-01-19 09:44:34 +10:00

trace.h

…

xlrbr.decode

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

xmips.decode

target/riscv: Add Xmipslsp instructions

2026-01-09 15:11:43 +10:00

xthead.decode

…

XVentanaCondOps.decode

…