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target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic

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riscv_imsic.c is the only caller.  Having it sitting in the TCG only
cpu_helper.c gets in the way of --disable-tcg for no good reason.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260703180538.3346781-24-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
2026-07-03 15:05:35 -03:00
committed by Alistair Francis
parent beecb30958
commit 6dd762b415
3 changed files with 11 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
hw/intc/riscv_imsic.c
View File

@@ -376,6 +376,17 @@ static void riscv_imsic_reset_enter(Object *obj, ResetType type)
}
}
static void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env,
privilege_mode_t priv,
aia_ireg_rmw_fn rmw_fn,
void *rmw_fn_arg)
{
if (priv <= PRV_M) {
env->aia_ireg_rmw_cb[priv] = rmw_fn;
env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg;
}
}
static void riscv_imsic_realize(DeviceState *dev, Error **errp)
{
RISCVIMSICState *imsic = RISCV_IMSIC(dev);

3
target/riscv/cpu.h
View File

@@ -680,9 +680,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
aia_ireg_rmw_fn rmw_fn,
void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
#endif /* !CONFIG_USER_ONLY */

10
target/riscv/tcg/cpu_helper.c
View File

@@ -590,16 +590,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value)
return old;
}
void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv,
aia_ireg_rmw_fn rmw_fn,
void *rmw_fn_arg)
{
if (priv <= PRV_M) {
env->aia_ireg_rmw_cb[priv] = rmw_fn;
env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg;
}
}
static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
bool virt)
{