Daniel Henrique Barboza 64ce9ac187 hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 ...

riscv-iommu spec: "If SADE is 1, the IOMMU updates A and D bits in
first-stage PTEs atomically. If SADE is 0, the IOMMU causes a
page-fault corresponding to the original access type if the
A bit is 0 or if the memory access is a store and the D bit is 0.".

Note that SADE=0 and A=0 will always cause a fault regardless of the
original access type.  Right now we're faulting in this case just for
reads.

Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3551
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Message-ID: <20260630211044.82894-1-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2026-07-01 20:14:20 +10:00

..

aia.c

hw/riscv/aia: Configure stride for the M-mode IMSIC

2026-07-01 19:59:10 +10:00

aia.h

hw/riscv/aia: Configure stride for the M-mode IMSIC

2026-07-01 19:59:10 +10:00

boot.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

boston-aia.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

cps.c

hw/riscv: Add support for RISCV CPS

2026-01-09 15:13:20 +10:00

fdt-common.c

hw/riscv: add create_fdt_plic() helper

2026-07-01 19:59:09 +10:00

k230.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

Kconfig

hw/riscv/atlantis: Add some i2c peripherals

2026-07-01 19:59:10 +10:00

meson.build

hw/riscv: Add Tenstorrent Atlantis machine

2026-07-01 19:59:10 +10:00

microblaze-v-generic.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

microchip_pfsoc.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

numa.c

hw/riscv/numa: make numa_enabled() public

2026-06-16 20:01:11 +10:00

opentitan.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

riscv_hart.c

target/riscv: Introduce externally facing CSR access functions

2026-06-15 13:10:15 +10:00

riscv-iommu-bits.h

hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set

2026-07-01 19:59:09 +10:00

riscv-iommu-hpm.c

hw/riscv/riscv-iommu: rename regs_rw to regs

2026-07-01 19:59:09 +10:00

riscv-iommu-hpm.h

…

riscv-iommu-pci.c

hw/riscv: Set IOMMU PAS via property

2026-02-25 23:46:04 +01:00

riscv-iommu-sys.c

include: move hw/sysbus.h to hw/core/

2025-12-27 10:11:08 +01:00

riscv-iommu.c

hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0

2026-07-01 20:14:20 +10:00

riscv-iommu.h

hw/riscv/riscv-iommu: rename regs_rw to regs

2026-07-01 19:59:09 +10:00

shakti_c.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

sifive_e.c

hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries

2026-05-27 08:05:25 +02:00

sifive_u.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

spike.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00

trace-events

…

trace.h

…

tt_atlantis.c

hw/riscv/atlantis: Add some i2c peripherals

2026-07-01 19:59:10 +10:00

virt-acpi-build.c

hw/riscv/aia: Provide number of irq sources

2026-07-01 19:59:10 +10:00

virt.c

hw/riscv/aia: Configure stride for the M-mode IMSIC

2026-07-01 19:59:10 +10:00

xiangshan_kmh.c

hw/riscv/boot: Account for discontiguous memory when loading firmware

2026-07-01 19:59:10 +10:00