Add a ppi_base parameter to tpm_build_ppi_acpi() instead of hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where PPI memory is dynamically allocated by the platform bus and the address is not known at compile time. Update the x86 callers (ISA TIS and CRB) to pass TPM_PPI_ADDR_BASE explicitly. No behavioral change. Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260327173209.148180-3-mbawa@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
203 lines
6.0 KiB
C
203 lines
6.0 KiB
C
/*
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* tpm_tis_isa.c - QEMU's TPM TIS ISA Device
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*
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* Copyright (C) 2006,2010-2013 IBM Corporation
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*
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* Authors:
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* Stefan Berger <stefanb@us.ibm.com>
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* David Safford <safford@us.ibm.com>
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*
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* Xen 4 support: Andrease Niederl <andreas.niederl@iaik.tugraz.at>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* Implementation of the TIS interface according to specs found at
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* http://www.trustedcomputinggroup.org. This implementation currently
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* supports version 1.3, 21 March 2013
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* In the developers menu choose the PC Client section then find the TIS
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* specification.
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*
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* TPM TIS for TPM 2 implementation following TCG PC Client Platform
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* TPM Profile (PTP) Specification, Family 2.0, Revision 00.43
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*/
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#include "qemu/osdep.h"
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#include "hw/isa/isa.h"
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#include "hw/core/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "hw/acpi/tpm.h"
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#include "tpm_prop.h"
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#include "tpm_tis.h"
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#include "qom/object.h"
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#include "hw/acpi/acpi_aml_interface.h"
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struct TPMStateISA {
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/*< private >*/
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ISADevice parent_obj;
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/*< public >*/
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TPMState state; /* not a QOM object */
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};
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OBJECT_DECLARE_SIMPLE_TYPE(TPMStateISA, TPM_TIS_ISA)
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static int tpm_tis_pre_save_isa(void *opaque)
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{
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TPMStateISA *isadev = opaque;
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return tpm_tis_pre_save(&isadev->state);
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}
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static const VMStateDescription vmstate_tpm_tis_isa = {
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.name = "tpm-tis",
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.version_id = 0,
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.pre_save = tpm_tis_pre_save_isa,
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.fields = (const VMStateField[]) {
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VMSTATE_BUFFER(state.buffer, TPMStateISA),
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VMSTATE_UINT16(state.rw_offset, TPMStateISA),
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VMSTATE_UINT8(state.active_locty, TPMStateISA),
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VMSTATE_UINT8(state.aborting_locty, TPMStateISA),
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VMSTATE_UINT8(state.next_locty, TPMStateISA),
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VMSTATE_STRUCT_ARRAY(state.loc, TPMStateISA, TPM_TIS_NUM_LOCALITIES, 0,
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vmstate_locty, TPMLocality),
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VMSTATE_END_OF_LIST()
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}
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};
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static void tpm_tis_isa_request_completed(TPMIf *ti, int ret)
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{
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TPMStateISA *isadev = TPM_TIS_ISA(ti);
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TPMState *s = &isadev->state;
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tpm_tis_request_completed(s, ret);
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}
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static enum TPMVersion tpm_tis_isa_get_tpm_version(TPMIf *ti)
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{
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TPMStateISA *isadev = TPM_TIS_ISA(ti);
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TPMState *s = &isadev->state;
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return tpm_tis_get_tpm_version(s);
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}
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static void tpm_tis_isa_reset(DeviceState *dev)
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{
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TPMStateISA *isadev = TPM_TIS_ISA(dev);
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TPMState *s = &isadev->state;
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return tpm_tis_reset(s, true);
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}
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static const Property tpm_tis_isa_properties[] = {
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DEFINE_PROP_UINT32("irq", TPMStateISA, state.irq_num, TPM_TIS_IRQ),
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DEFINE_PROP_TPMBE("tpmdev", TPMStateISA, state.be_driver),
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};
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static void tpm_tis_isa_initfn(Object *obj)
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{
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TPMStateISA *isadev = TPM_TIS_ISA(obj);
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TPMState *s = &isadev->state;
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memory_region_init_io(&s->mmio, obj, &tpm_tis_memory_ops,
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s, "tpm-tis-mmio",
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TPM_TIS_NUM_LOCALITIES << TPM_TIS_LOCALITY_SHIFT);
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}
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static void tpm_tis_isa_realizefn(DeviceState *dev, Error **errp)
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{
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TPMStateISA *isadev = TPM_TIS_ISA(dev);
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TPMState *s = &isadev->state;
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if (!tpm_find()) {
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error_setg(errp, "at most one TPM device is permitted");
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return;
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}
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if (!s->be_driver) {
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error_setg(errp, "'tpmdev' property is required");
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return;
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}
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if (s->irq_num > 15) {
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error_setg(errp, "IRQ %d is outside valid range of 0 to 15",
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s->irq_num);
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return;
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}
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s->irq = isa_get_irq(ISA_DEVICE(dev), s->irq_num);
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memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)),
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TPM_TIS_ADDR_BASE, &s->mmio);
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tpm_ppi_init(&s->ppi, isa_address_space(ISA_DEVICE(dev)),
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TPM_PPI_ADDR_BASE, OBJECT(dev));
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}
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static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
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{
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Aml *dev, *crs;
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TPMStateISA *isadev = TPM_TIS_ISA(adev);
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TPMIf *ti = TPM_IF(isadev);
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dev = aml_device("TPM");
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if (tpm_tis_isa_get_tpm_version(ti) == TPM_VERSION_2_0) {
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aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
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aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
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} else {
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
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}
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aml_append(dev, aml_name_decl("_UID", aml_int(1)));
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aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
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crs = aml_resource_template();
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aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, TPM_TIS_ADDR_SIZE,
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AML_READ_WRITE));
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/*
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* FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
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* fix default TPM_TIS_IRQ value there to use some unused IRQ
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*/
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/* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */
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aml_append(dev, aml_name_decl("_CRS", crs));
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tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);
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aml_append(scope, dev);
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}
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static void tpm_tis_isa_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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TPMIfClass *tc = TPM_IF_CLASS(klass);
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AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
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device_class_set_props(dc, tpm_tis_isa_properties);
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dc->vmsd = &vmstate_tpm_tis_isa;
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tc->model = TPM_MODEL_TPM_TIS;
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tc->ppi_enabled = true;
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dc->realize = tpm_tis_isa_realizefn;
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device_class_set_legacy_reset(dc, tpm_tis_isa_reset);
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tc->request_completed = tpm_tis_isa_request_completed;
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tc->get_version = tpm_tis_isa_get_tpm_version;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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adevc->build_dev_aml = build_tpm_tis_isa_aml;
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}
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static const TypeInfo tpm_tis_isa_info = {
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.name = TYPE_TPM_TIS_ISA,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(TPMStateISA),
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.instance_init = tpm_tis_isa_initfn,
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.class_init = tpm_tis_isa_class_init,
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.interfaces = (const InterfaceInfo[]) {
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{ TYPE_TPM_IF },
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{ TYPE_ACPI_DEV_AML_IF },
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{ }
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}
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};
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static void tpm_tis_isa_register(void)
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{
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type_register_static(&tpm_tis_isa_info);
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}
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type_init(tpm_tis_isa_register)
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