Commit Graph

305 Commits

Author SHA1 Message Date
Magnus Kulke
d564c2a296 target/i386/mshv: use generic FPU/xcr0 state
Instead of using an mshv-specific FPU state representation we switch to
the generic i386 representation of the registers.

Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260417105618.3621-3-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-06-25 19:08:45 +02:00
Magnus Kulke
a6961182bc target/i386/mshv: use arch_load/store_reg fns
Improved consistency around the naming of load/store register fn's. this
is required since we want to roundtrip more registers in a migration
than what's currently required for MMIO emulation.

Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260417105618.3621-2-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-06-25 19:08:44 +02:00
Magnus Kulke
e7c9532d89 accel/mshv: disable la57 (5lvl paging)
This change disable la57 paging on the mshv hypervisor on both the
mshv processor feature bitmap and mask the cpuid feature leaf to the
guest.

Since the removal of hypervisor-assisted gva=>gpa translation in
1c85a4a3d7 we have seen MMIO errors in guests on la57-enabled hw. We
will have to investigate and test this further.

Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Reviewed-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
Reviewed-by: Wei Liu <wei.liu@kernel.org>
Reviewed-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260416121116.527927-10-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-06-25 19:08:12 +02:00
Magnus Kulke
38a557bc85 target/i386: query mshv accel for supported cpuids
We implement mshv_get_supported_cpuid() and invoke it in
x86_cpu_get_supported_feature_word() retrieve the cpu features that the
host is supporting. Initially we mask the virtualization capabilitities
potentially we might need to mask more in the future.

Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Reviewed-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260416121116.527927-7-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-06-25 19:08:12 +02:00
Philippe Mathieu-Daudé
e5590b5378 accel/hvf: Reduce hvf_kernel_irqchip_override scope
hvf_kernel_irqchip_override is only used within the
accel/hvf/hvf-all.c file, no need to expose the symbol.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Message-Id: <20260613145356.88410-1-philmd@oss.qualcomm.com>
2026-06-18 14:27:21 +02:00
Philippe Mathieu-Daudé
cb30b8758d system: Move cpu_physical_memory_*() declarations to 'system/physmem.h'
The following cpu_physical_memory_*() methods do not involve any
vCPU but only access physical memory:

 - cpu_physical_memory_read()
 - cpu_physical_memory_write()
 - cpu_physical_memory_map()
 - cpu_physical_memory_unmap()

Rename them removing the 'cpu_' prefix, and move then to the
"system/physmem.h" header with the other methods involved in
global physical address space.

Mechanical change using sed, then adding missing headers manually.

No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020839.19104-7-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Philippe Mathieu-Daudé
77293ecc95 system/memory: Constify various MemoryRegionCache arguments
Mark the MemoryRegionCache structure const when it is only
accessed read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-7-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Philippe Mathieu-Daudé
47b23339a5 system/memory: Constify various AddressSpace arguments (access)
Mark the AddressSpace structure const when it is only accessed
read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-6-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Philippe Mathieu-Daudé
7c862a8a45 system/memory: Constify various AddressSpace arguments (cache)
Mark the AddressSpace structure const when it is only accessed
read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-5-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Philippe Mathieu-Daudé
e8d053f4de system/memory: Constify various AddressSpace arguments (notify)
Mark the AddressSpace structure const when it is only accessed
read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-4-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Philippe Mathieu-Daudé
ff7ebb3d5e system/memory: Constify various AddressSpace arguments (checks)
Mark the AddressSpace structure const when it is only accessed
read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-2-philmd@oss.qualcomm.com>
2026-06-18 14:27:04 +02:00
Stefan Hajnoczi
665f1a0904 Merge tag 'pull-target-arm-20260616' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
 * Implementation of various insns preparatory to FEAT_SVE2p2
 * hw/arm/smmuv3: Make smmuv3 ATS, RIL, SSIDSIZE, and OAS 'auto' properties work
 * hw/pci/pci: Enforce pci_setup_iommu_per_bus() is called only once per bus
 * hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3
 * target/arm: honour CCR.BFHFNMIGN for probed data BusFaults
 * hw/arm/bcm2838: Route I2C interrupts to GIC

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# gpg: Signature made Tue 16 Jun 2026 15:05:17 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260616' of https://gitlab.com/pm215/qemu: (61 commits)
  target/arm: Implement floating-point log and convert to integer (zeroing)
  target/arm: Implement SVE floating-point convert (top, predicated, zeroing)
  target/arm: Enable zeroing in DO_FCVT{N, L}T macros in sve_helper.c
  target/arm: Implement FRINT{32,64}{X,Z}
  target/arm: Implement SCVTF, UCVTF (predicated, zeroing)
  target/arm: Implement Floating-point square root (predicated, zeroing)
  target/arm: Implement Floating-point convert (predicated, zeroing)
  target/arm: Implement Floating-point round to integral value (predicated, zeroing)
  target/arm: Add data argument to do_frint_mode
  target/arm: Implement SVE2 integer unary operations (predicated, zeroing)
  target/arm: Implement SVE reverse doublewords (zeroing)
  target/arm: Implement SVE reverse within elements (zeroing)
  target/arm: Implement SVE bitwise unary operations (predicated, zeroing)
  target/arm: Implement SVE integer unary operations (predicated, zeroing)
  target/arm: Expand DO_ZPZ in translate-sve.c
  target/arm: Enable zeroing in DO_ZPZ macros in sve_helper.c
  target/arm: Rename sve unary predicated patterns
  target/arm: Add feature predicates for SVE2.2 and SME2.2
  hw/arm/bcm2838: Route I2C interrupts to GIC
  target/arm: honour CCR.BFHFNMIGN for probed data BusFaults
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-17 10:17:03 -04:00
Shameer Kolothum
11b9798c7b memory: Allow RAM device regions to skip IOMMU mapping
Some RAM device regions created with memory_region_init_ram_device_ptr()
are not intended to be P2P DMA targets.

The VFIO listener currently treats all RAM device regions as DMA
capable and attempts to map them into the IOMMU. For regions without
dma-buf backing this fails and prints warnings such as:

  IOMMU_IOAS_MAP failed: Bad address, PCI BAR?

Introduce a MemoryRegion flag (ram_device_skip_iommu_map) to mark RAM
device regions that should not be IOMMU mapped, paired with
memory_region_skip_iommu_map() / memory_region_set_skip_iommu_map()
accessors. When the flag is set, the VFIO listener skips DMA mapping
for that region.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Message-id: 20260609112552.378999-21-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-16 11:06:46 +01:00
Shameer Kolothum
9e67a50ea9 system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq
The viommu field is assigned but never used. Callers freeing the
veventq already have access to the IOMMUFDViommu object through other
references, so this field is redundant.

Removing it also simplifies upcoming changes where veventq is
allocated based on the viommu id before the IOMMUFDViommu object is
created (e.g. vendor CMDQV-based veventq allocation).

No functional change.

Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20260609112552.378999-6-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-16 11:06:46 +01:00
Nicolin Chen
b391e41e53 backends/iommufd: Introduce iommufd_backend_viommu_mmap
Add a backend helper to mmap hardware MMIO regions exposed via iommufd for
a vIOMMU instance. This allows user space to access HW-accelerated MMIO
pages provided by the vIOMMU.

The caller is responsible for unmapping the returned region.

Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20260609112552.378999-5-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-16 11:06:46 +01:00
Nicolin Chen
41dae463f4 backends/iommufd: Introduce iommufd_backend_alloc_hw_queue
Add a helper to allocate an iommufd backed HW queue for a vIOMMU.

While at it, define a struct IOMMUFDHWqueue for use by vendor
implementations.

Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20260609112552.378999-4-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-16 11:06:46 +01:00
Nicolin Chen
d2f3b3156d backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr
The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data
buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend
iommufd_backend_alloc_viommu() to pass a user pointer and size to the
kernel.

Update the caller accordingly.

Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20260609112552.378999-3-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-16 11:06:46 +01:00
Stefan Hajnoczi
dfd6387bf9 Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
pci, vhost, virtio, iommu: features, fixes, cleanups

intel_iommu:
    PASID support for passthrough
    some properties renamed
virtio-rtc:
    new device
acpi:
    watchdog (x86 q35)
    COM irqs are now shared
vhost-user:
    vhost-user passes GPA not HVA now
    vhost SHMEM_MAP/UNMAP support
vhost-vdpa:
    svq IN_ORDER support
amd_iommu:
    IOMMU XT interrupt support
    command buffer fixes
cxl:
    PPR support
    performant path for non-interleaved cases
vhost-scsi:
    build fix for older kernel headers
fixes, cleanups all over the place

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (106 commits)
  hw/scsi/vhost-scsi: fix build with older kernel headers
  tests/qtest: add 8-byte MMIO access sweep for intel-iommu
  intel_iommu: fix guest-triggerable abort on oversized MMIO access
  hw/cxl: Add a performant (and correct) path for the non interleaved cases
  hw/cxl: Allow cxl_cfmws_find_device() to filter on whether interleaved paths are accepted
  hw/cxl/events: Fix handling of component ID in event records generation to not assume it is a string
  hw/cxl: Add fixes in Post Package Repair (PPR)
  hw/cxl: Fix handling of component ID to not assume it is a string
  vhost-user.rst: fix typo
  vhost-user-device: Add shared memory BAR
  qmp: add shmem feature map
  vhost_user.rst: Add GET_SHMEM_CONFIG message
  vhost_user: Add frontend get_shmem_config command
  vhost_user.rst: Add SHMEM_MAP/_UNMAP to spec
  vhost_user.rst: Align VhostUserMsg excerpt members
  vhost-user: Add VirtIO Shared Memory map request
  tests: acpi: x86/q35: update expected WDAT blob
  tests: acpi: x86/q35: add WDAT table test case
  tests: acpi: x86/q35: whitelist new WDAT table
  x86: q35: generate WDAT ACPI table
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-15 16:47:02 -04:00
Albert Esteve
b52e1896e7 vhost-user: Add VirtIO Shared Memory map request
Add SHMEM_MAP/UNMAP requests to vhost-user for dynamic management of
VIRTIO Shared Memory mappings.

This implementation introduces VirtioSharedMemoryMapping as a unified
QOM object that manages both the mapping metadata and MemoryRegion
lifecycle. This object provides reference-counted lifecycle management
with automatic cleanup of file descriptors and memory regions
through QOM finalization.

This request allows backends to dynamically map file descriptors into a
VIRTIO Shared Memory Region identified by their shmid. Maps are created
using memory_region_init_ram_from_fd() with configurable read/write
permissions, and the resulting MemoryRegions are added as subregions to
the shmem container region. The mapped memory is then advertised to the
guest VIRTIO drivers as a base address plus offset for reading and
writting according to the requested mmap flags.

The backend can unmap memory ranges within a given VIRTIO Shared Memory
Region to free resources. Upon receiving this message, the frontend
removes the MemoryRegion as a subregion and automatically unreferences
the VirtioSharedMemoryMapping object, triggering cleanup if no other
references exist.

Error handling has been improved to ensure consistent behavior across
handlers that manage their own vhost_user_send_resp() calls. Since
these handlers clear the VHOST_USER_NEED_REPLY_MASK flag, explicit
error checking ensures proper connection closure on failures,
maintaining the expected error flow.

Note the memory region commit for these operations needs to be delayed
until after we reply to the backend to avoid deadlocks. Otherwise,
the MemoryListener would send a VHOST_USER_SET_MEM_TABLE message
before the reply.

Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260304165223.2166175-2-aesteve@redhat.com>
2026-06-03 08:36:42 -04:00
Zhenzhong Duan
c579197d6b intel_iommu: Refactor PASID processing to use IOMMU_NO_PASID internally
The PCI subsystem uses PCI_NO_PASID for requests-without-PASID, but VT-d
emulation uses IOMMU_NO_PASID internally (ecap.RPS==0). This leads to
conversion and checking code between PCI_NO_PASID and IOMMU_NO_PASID
throughout the implementation.

Refactor to use IOMMU PASID consistently within Intel IOMMU by storing
IOMMU PASID value in vtd_as->pasid. After this change, PCI_NO_PASID is
only used at three boundary points:

1. PCI_NO_PASID -> IOMMU_NO_PASID: Convert PCI PASID to IOMMU PASID in
   vtd_find_add_as() and cache in vtd_as->pasid.
2. IOMMU_NO_PASID -> PCI_NO_PASID: Convert when notifying UNMAP events
   via memory_region_notify_iommu() and returning IOMMUTLBEntry in
   vtd_iommu_translate().

This eliminates conversion/checks in PASID table lookups, simplifies
invalidation logic with consistent PASID values, and improves code
readability. The PCI subsystem interface remains unchanged to maintain
compatibility with other IOMMU implementations that may not use PASID 0
for requests-without-PASID.

Suggested-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260527054658.1021096-11-zhenzhong.duan@intel.com>
2026-06-03 08:36:11 -04:00
Zhenzhong Duan
20fb2f6961 iommufd: Extend attach/detach_hwpt callbacks to support pasid
Same for the two wrappers and their call sites.

Suggested-by: Shameer Kolothum Thodi <skolothumtho@nvidia.com>
Suggested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260527054658.1021096-3-zhenzhong.duan@intel.com>
2026-06-03 08:36:11 -04:00
Akihiko Odaki
a0f5963a30 ui/input: Introduce QemuInputEvent typedef
Add QemuInputEvent as the input subsystem's name for InputEvent and use
it in input handler, queue, and replay interfaces.

This prepares for decoupling QEMU's internal input event representation
from the QAPI InputEvent type.

Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-1-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
2026-05-25 01:00:54 +04:00
Kevin Wolf
53074ba033 block: Add flags parameter to blk_*_pdiscard()
All existing callers pass 0, but we need a way to pass BDRV_REQ_NO_QUEUE
for discard requests.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20260421161132.99878-4-kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2026-05-19 17:25:48 +02:00
Kevin Wolf
34a6763776 block: Add blk_co_start/end_request() and BDRV_REQ_NO_QUEUE
If a device uses blk_inc/dec_in_flight() in order to build macro
operations that involve multiple requests for the block layer and that
need to be completed as a unit before the BlockBackend can be considered
drained, it sets the stage for a deadlock: When a drain is requested,
the inner request at the BlockBackend level will be queued in
blk_wait_while_drained() and wait until the drained section ends, but at
the same time, drain_begin can only return if the whole macro operation
at the device level has completed.

Introduce a new interface to allow implementing the logic correctly:
Instead of queueing individual requests, blk_co_start_request() calls
blk_wait_while_drained() once at the beginning. The individual requests
must then set BDRV_REQ_NO_QUEUE to avoid being queued and running into
the deadlock; being wrapped in blk_co_start/end_request() makes sure
that drain_begin waits for them and they don't sneak in when the
BlockBackend is supposed to already be quiescent.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20260421161132.99878-3-kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2026-05-19 17:25:48 +02:00
Scott J. Goldman
a86024eb2d target/arm/hvf: Fix WFI halting to stop idle vCPU spinning
Commit b5f8f77271 ("accel/hvf: Implement WFI without using pselect()")
changed hvf_wfi() from blocking the vCPU thread with pselect() to
returning EXCP_HLT, intending QEMU's main event loop to handle the
idle wait. However, cpu->halted was never set, so cpu_thread_is_idle()
always returns false and the vCPU thread spins at 100% CPU per core
while the guest is idle.

Fix this by:

1. Setting cpu->halted = 1 in hvf_wfi() so the vCPU thread sleeps on
   halt_cond in qemu_process_cpu_events().

2. Arming a per-vCPU QEMU_CLOCK_VIRTUAL timer to fire when the guest's
   virtual timer (CNTV_CVAL_EL0) would expire. This is necessary
   because HVF only delivers HV_EXIT_REASON_VTIMER_ACTIVATED during
   hv_vcpu_run(), which is not called while the CPU is halted. The
   timer callback mirrors the VTIMER_ACTIVATED handler: it raises the
   vtimer IRQ through the GIC and marks vtimer_masked, causing the
   interrupt delivery chain to wake the vCPU via qemu_cpu_kick().

3. Clearing cpu->halted in hvf_arch_vcpu_exec() when cpu_has_work()
   indicates a pending interrupt, and cancelling the WFI timer.

4. Re-arming the WFI timer from hvf_vm_state_change() on the resume
   transition for any halted vCPU, since the QEMUTimer is per-instance
   state and is not migrated. After cpu_synchronize_all_states() the
   migrated vtimer state is mirrored in env, so we can read CNTV_CTL
   and CNTV_CVAL from there. If the vtimer has already expired by the
   time the destination resumes, hvf_wfi_timer_cb() is invoked
   directly so the halted vCPU is woken up.

All wfi_timer handling (allocation, arming, deletion, and the resume
re-arm) is gated on !hvf_irqchip_in_kernel(): with the Apple in-kernel
vGIC, HVF owns the vtimer and delivers wake-ups itself.

Note for stable backports: this commit won't apply to 11.0 as
it has changes to handle the hvf in-kernel irqchip support that
landed after the 11.0 release. The v3 version of this commit:
  https://patchew.org/QEMU/20260427195516.46256-1-scottjgo@gmail.com/
should be suitable for 11.0 backporting (it is essentially
identical except that it doesn't make the changes conditional
on !hvf_irqchip_in_kernel()).

Cc: qemu-stable@nongnu.org
Fixes: b5f8f77271 ("accel/hvf: Implement WFI without using pselect()")
Signed-off-by: Scott J. Goldman <scottjgo@gmail.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
[PMM: added note about stable backports to commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-15 09:55:25 +01:00
Philippe Mathieu-Daudé
bea27e8264 system/kvm_xen: Include missing 'exec/target_page.h' header
The "exec/target_page.h" header is indirectly included. Include
it explicitly otherwise we get when refactoring unrelated headers:

  include/system/kvm_xen.h:41:55: error: ‘TARGET_PAGE_BITS’ undeclared (first use in this function)
     41 | #define XEN_SPECIAL_PFN(x) ((XEN_SPECIAL_AREA_ADDR >> TARGET_PAGE_BITS) + \
        |                                                       ^~~~~~~~~~~~~~~~

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260313062055.2188-16-philmd@linaro.org>
2026-05-06 12:37:33 +02:00
Mohamed Mediouni
37863fff59 hvf: arm: enable vGIC by default for virt-11.1 and later
Save states are incompatible between kernel-irqchip=on and off on HVF due to opaque vGIC state.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-id: 20260429190532.26538-16-mohamed@unpredictable.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-05 09:30:12 +01:00
Mohamed Mediouni
d7a75ea483 hw/arm, target/arm: nested virtualisation on HVF
Add hvf_arm_el2_supported for querying EL2 availability.
An hvf_nested_virt_enable workaround is added as nested virt has
to be enabled early on HVF.

And adds hvf_nested_virt_enabled.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-id: 20260429190532.26538-6-mohamed@unpredictable.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-05 09:25:21 +01:00
Mohamed Mediouni
2a3c965516 accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC
Misc changes needed for HVF vGIC enablement.

Note: x86_64 macOS exposes interrupt controller virtualisation since macOS 12.
Keeping an #ifdef here in case we end up supporting that...

However, given that x86_64 macOS is on its way out, it'll probably (?)
not be supported in QEMU.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Message-id: 20260429190532.26538-4-mohamed@unpredictable.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-05 09:25:21 +01:00
Stefan Hajnoczi
ac0cc20ad2 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* hw/qdev: Consolidate qdev_get_printable_name() into qdev_get_human_name()
* target/i386: add new models for GMET, MMIO/GDS/RFDS mitigation and MBEC
* whpx improvements
* bump meson to 1.11.1
* tests: add test for json-streamer.c error recovery
* kconfig cleanups
* target/arm/hvf, target/i386/hvf: Pass MR-relative offset to memory_region_set_dirty()

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# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
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# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (58 commits)
  whpx: i386: documentation update
  whpx: i386: add SeparateSecurityDomain flag and make default
  whpx: i386: add feature to intercept #GP MSR accesses
  whpx: i386: update migration blocker message
  whpx: i386: set APIC ID only when APIC present
  whpx: xsave support
  target/i386: add de/compaction to xsave_helper
  target/i386: make xsave_buf present unconditionally
  target/i386: emulate: use exception_payload for fault address
  whpx: i386: Pause VM on fatal exception to be able to inspect state
  whpx: i386: set WHvX64RegisterInitialApicId
  whpx: i386: some x2APIC awareness
  whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip
  target: i386: HLT type that ignores EFLAGS.IF
  whpx: i386: ignore vpassist when kernel-irqchip=off
  whpx: i386: tighten APIC base validity check
  target/i386: emulate, hvf: rdmsr/wrmsr GPF handling
  whpx: i386: don't increment eip on MSR access raising GPF
  whpx: i386: unknown MSR configurability
  whpx: i386: enable GuestIdleReg enlightenment
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-01 14:41:49 -04:00
Mohamed Mediouni
a1a3692d15 whpx: i386: add SeparateSecurityDomain flag and make default
For workloads where isolation is less important, -accel whpx,ssd=off
will provide significantly higher MMIO performance.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-37-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:04 +02:00
Mohamed Mediouni
bb605df21e whpx: i386: add feature to intercept #GP MSR accesses
It turns out they're not that uncommon, so have
a feature around to log those.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-35-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:04 +02:00
Mohamed Mediouni
cfaa3b6c95 whpx: xsave support
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-30-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:04 +02:00
Mohamed Mediouni
d9225244af whpx: i386: unknown MSR configurability
Add an option to inject back a GPF for unknown MSRs.

Keep it on by default for now as Linux expects accesses to some
AMD-specific MSRs to always succeed when on an AMD host.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-18-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:03 +02:00
Mohamed Mediouni
478e27cf87 whpx: i386: fix CPUID[1:EDX].APIC reporting
Hyper-V always has CPUID[1:EDX].APIC set, even when the APIC isn't enabled yet.

Work around this by also using the APICBASE trap for kernel-irqchip=on.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-16-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:03 +02:00
Mohamed Mediouni
77f90aef5b whpx: i386: kernel-irqchip=off fixes
This was really... quite broken. After fixing this,
Windows boots with kernel-irqchip=off.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-9-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:03 +02:00
Mohamed Mediouni
f741457c1a whpx: i386: reintroduce enlightenments for Windows 10
Was removed in 2c08624 but it's still useful for
Windows 10 so reintroduce it there.

And this time, actually make it work by reporting
the hypervisor bit in CPUID.

Pretend to be vmware to be able to use vmport's functionality.

If the vmware frequency leaf is disabled, pretend to be
KVM, with the only capability reported being X2APIC support.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-7-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:03 +02:00
Mohamed Mediouni
057143ba75 whpx: i386: wire up feature probing
Windows 10 doesn't have the API for this, so using this
only for Windows 11.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-4-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-04-30 17:55:03 +02:00
Jaehoon Kim
9fea80ddf0 qapi/iothread: introduce poll-weight parameter for aio-poll
Introduce a configurable poll-weight parameter for adaptive polling
in IOThread. This parameter replaces the hardcoded POLL_WEIGHT_SHIFT
constant, allowing runtime control over how much the most recent
event interval affects the next polling duration calculation.

The poll-weight parameter uses a shift value where larger values
decrease the weight of the current interval, enabling more gradual
adjustments. When set to 0, a default value of 3 is used (meaning
the current interval contributes approximately 1/8 to the weighted
average).

This patch also removes the hardcoded default value checks from
adjust_polling_time(). Instead, poll-grow, poll-shrink, and
poll-weight now use default values initialized in iothread.c
during IOThread creation.

Signed-off-by: Jaehoon Kim <jhkim@linux.ibm.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20260423195918.661299-4-jhkim@linux.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-04-29 11:31:44 -04:00
Philippe Mathieu-Daudé
712e2b9aa8 system/memory: Constify various AddressSpace arguments (flatview)
Mark the AddressSpace structure const when it is only accessed
read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260319191017.12636-2-philmd@linaro.org>
2026-04-24 21:20:44 +02:00
Philippe Mathieu-Daudé
3912e312ae hw/tpm: Simplify tpm_ppi_enabled()
TPM instances don't expose any "ppi" property anymore,
remove that dead code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-6-philmd@linaro.org>
2026-04-24 21:20:44 +02:00
Philippe Mathieu-Daudé
6f4a959952 hw/tpm: Add TPMIfClass::ppi_enabled field
Each TPM derived device has a @ppi_enabled field, itself
exposed as a QOM property. External layers (like the ACPI
subsystem) wanting to know whether a device implements PPI
has to check for the QOM property available. This can be
simplified by declaring a single field in the TPM interface.

Here we add such field to TPMIfClass, before converting each
TPM devices to use it in the following commits.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-3-philmd@linaro.org>
2026-04-24 21:20:44 +02:00
Philippe Mathieu-Daudé
60ab4a0437 hw/tpm: Factor tpm_ppi_enabled() out
Factor out tpm_ppi_enabled() before modifying it in a unique place.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-2-philmd@linaro.org>
2026-04-24 21:20:44 +02:00
Zhenzhong Duan
e2b7310276 iommufd: Rename all the idev and idevc variables to hiod and hiodc
We used idev and idevc naming for HostIOMMUDeviceIOMMUFD and corresponding
class variables which followed the iommufd_device naming in linux kernel.

This is mixed with the hiod naming for base type HostIOMMUDevice. Rename
HostIOMMUDeviceIOMMUFD* to hiodi* for consistency in QEMU.

No functional change intended.

Suggested-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260401080354.1347212-1-zhenzhong.duan@intel.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
2026-04-21 18:28:42 +02:00
Luigi Leonardi
9b4edc3eca igvm: fix parent object type in IgvmCfg struct
IgvmCfg is defined as an Object but, currently, its first member is an
ObjectClass.

Replace ObjectClass with Object.

Fixes: c1d466d267 ("backends/igvm: Add IGVM loader and configuration")
Signed-off-by: Luigi Leonardi <leonardi@redhat.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Message-ID: <20260330-igvm_fixes-v1-3-03587a5a808b@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2026-03-31 08:53:47 +02:00
Paolo Bonzini
c725a896c6 typedefs: move QIgvm out of typedefs.h
Typedefs.h should only be used for really core types; QIgvm is
just an opaque struct that is defined in system/igvm-internal.h,
and the typedef itself can be placed simply in system/igvm.h.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-03-12 12:02:55 +01:00
Peter Maydell
ae56950eac Merge tag 'firmware-20260310-pull-request' of https://gitlab.com/kraxel/qemu into staging
- firmware.json spec update for svsm.
- igvm bugfixes.

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# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
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* tag 'firmware-20260310-pull-request' of https://gitlab.com/kraxel/qemu:
  i386/sev/igvm: do not reset guest policy if IGVM does not set it
  igvm: fix build when igvm is not installed in a well known path
  docs/interop: Add AMD SEV-SNP SVSM interface to firmware.json

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 13:32:30 +00:00
Peter Maydell
89851dbcce Merge tag 'accel-tcg-20260310' of https://github.com/philmd/qemu into staging
Accelerators and TCG patches queue

- Improve TCG extract and deposit
- Build accelerator stub files once

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# gpg: Signature made Tue Mar 10 10:44:26 2026 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'accel-tcg-20260310' of https://github.com/philmd/qemu:
  accel/qtest: Build once as common object
  accel/xen: Build without target-specific knowledge
  accel/hvf: Build without target-specific knowledge
  accel/mshv: Build without target-specific knowledge
  accel/mshv: Forward-declare mshv_root_hvcall structure
  accel/stubs: Build stubs once
  accel/kvm: Make kvm_irqchip*notifier() declaration non target-specific
  accel/kvm: Include missing 'exec/cpu-common.h' header
  target/hppa: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64()
  tcg/optimize: possibly expand deposit into zero with shifts
  tcg: target-dependent lowering of extract to shr/and
  tcg: Add tcg_op_imm_match
  tcg: Expand missing rotri with extract2
  tcg/optimize: Lower unsupported extract2 during optimize
  tcg/optimize: Lower unsupported deposit during optimize
  tcg: Drop extract+shl expansions in tcg_gen_deposit_z_*

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 13:32:04 +00:00
Peter Maydell
56fe2ca5b6 Merge tag 'staging-pull-request' of https://gitlab.com/peterx/qemu into staging
Memory pull for 11.0 softfreeze

- BALATON's memory cleanups on _nomigrate MRs and else
- Phil's small constify series and else
- Marc-André's initial cleanup patches around ram discard manager

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# gpg: Signature made Mon Mar  9 20:38:51 2026 GMT
# gpg:                using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706
# gpg:                issuer "peterx@redhat.com"
# gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal]
# gpg:                 aka "Peter Xu <peterx@redhat.com>" [marginal]
# gpg: WARNING: The key's User ID is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D  D1A9 3B5F CCCD F3AB D706

* tag 'staging-pull-request' of https://gitlab.com/peterx/qemu:
  system/memory: Have memory_region_type() correctly describe containers
  system/xen: Constify various MemoryRegion arguments
  system/memory: Constify various MemoryRegion arguments
  system/ramblock: Constify various RAMBlock arguments
  kvm: replace RamDicardManager by the RamBlockAttribute
  system/memory: minor doc fix
  virtio-mem: use warn_report_err_once()
  memory: drop RamDiscardListener::double_discard_supported
  system/rba: use DIV_ROUND_UP
  memory: Factor out common ram ptr initialization
  memory: Factor out common ram region initialization
  memory: Add internal memory_region_register_ram function
  memory: Shorten memory_region_init_ram_device_ptr and memory_region_init_rom_device
  memory: Remove memory_region_init_ram_nomigrate()
  hw/xtensa/xtfpga: Do not use memory_region_init_ram_nomigrate()
  sun4m,sun4u,tcx: Do not use memory_region_init_ram_nomigrate()
  memory: Remove memory_region_init_rom_nomigrate()
  hw/display/{cg3.tcx}: Do not use memory_region_init_rom_nomigrate()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 11:38:58 +00:00
Philippe Mathieu-Daudé
591357b68f accel/mshv: Forward-declare mshv_root_hvcall structure
Forward-declare the target-specific mshv_root_hvcall structure
in order to keep 'system/mshv_int.h' target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-3-philmd@linaro.org>
2026-03-10 11:36:21 +01:00