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target/alpha: Introduce alpha_phys_addr_space_bits()

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In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a
a runtime function to correctly represent the size of the physical
address space for EV4-6 based on the current CPU version.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20260112-phys_addr-v3-1-5f90fdb4015f@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Anton Johansson
2026-01-12 13:22:42 +01:00
committed by Philippe Mathieu-Daudé
parent 62e8edfe1b
commit f5fa259b50
1 changed files with 22 additions and 1 deletions
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23
linux-user/alpha/target_proc.h
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@@ -6,6 +6,27 @@
#ifndef ALPHA_TARGET_PROC_H
#define ALPHA_TARGET_PROC_H
#include "qemu/osdep.h"
#include "target/alpha/cpu.h"
static uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env)
{
switch (env->implver) {
case IMPLVER_2106x:
/* EV4 */
return 34;
case IMPLVER_21164:
/* EV5 */
return 40;
case IMPLVER_21264:
case IMPLVER_21364:
/* EV6 and EV7*/
return 44;
default:
g_assert_not_reached();
}
}
static int open_cpuinfo(CPUArchState *cpu_env, int fd)
{
int max_cpus = sysconf(_SC_NPROCESSORS_CONF);
@@ -57,7 +78,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
"L1 Dcache\t\t: n/a\n"
"L2 cache\t\t: n/a\n"
"L3 cache\t\t: n/a\n",
model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS,
model, TARGET_PAGE_SIZE, alpha_phys_addr_space_bits(cpu_env),
max_cpus, num_cpus, cpu_mask);
return 0;