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Merge tag 'pull-target-arm-20260407' of https://gitlab.com/pm215/qemu into staging

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target-arm queue:
 * docs/system: remove extraneous sentence
 * target/arm: fix fault_s1ns for stage 2 faults
 * target/arm: do_ats_write(): avoid assertion when ptw failed

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# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260407' of https://gitlab.com/pm215/qemu:
  docs/system: remove extraneous sentence
  target/arm: fix fault_s1ns for stage 2 faults
  target/arm: do_ats_write(): avoid assertion when ptw failed

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2026-04-07 18:55:04 +01:00
parent b6a7d06213 8a9fa9ec99
commit e29302cbe6
4 changed files with 15 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
docs/system/introduction.rst
View File

@@ -165,10 +165,8 @@ names so we can override the defaults later.
-m 4096 \
We then define the 4 vCPUs using the ``max`` option which gives us all
the Arm features QEMU is capable of emulating. We enable a more
emulation friendly implementation of Arm's pointer authentication
algorithm. We explicitly specify TCG acceleration even though QEMU
would default to it anyway.
the Arm features QEMU is capable of emulating. We explicitly specify
TCG acceleration even though QEMU would default to it anyway.
.. code::

5
target/arm/internals.h
View File

@@ -740,7 +740,10 @@ typedef enum ARMGPCF {
* @paddr_space: physical address space that caused a fault for gpc
* @stage2: True if we faulted at stage 2
* @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
* @s1ns: True if we faulted on a non-secure IPA while in secure state
* @s1ns: True if we faulted on a non-secure IPA. Note that (unlike the
* HPFAR_EL2.NS bit) this is set for any stage 2 fault for an NS IPA, so
* code must check that this is for a fault taken to Secure EL2 before
* propagating s1ns to HPFAR_EL2.NS.
* @ea: True if we should set the EA (external abort type) bit in syndrome
*/
typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;

12
target/arm/ptw.c
View File

@@ -611,12 +611,14 @@ static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx)
{
/*
* For stage 2 faults in Secure EL22, S1NS indicates
* whether the faulting IPA is in the Secure or NonSecure
* IPA space. For all other kinds of fault, it is false.
* For stage 2 faults, S1NS indicates whether the faulting IPA is
* in the Non-Secure (true) or Secure (false) IPA space. For all
* other kinds of fault, it is false. Note that we do not
* distinguish "s2 fault on NS IPA taken to Secure EL2" from
* "s2 fault on NS IPA taken to NS EL2 or Realm EL2" here, but
* instead do that when setting HPFAR_EL2.NS.
*/
return space == ARMSS_Secure && regime_is_stage2(s2_mmu_idx)
&& s2_mmu_idx == ARMMMUIdx_Stage2_S;
return space == ARMSS_NonSecure && regime_is_stage2(s2_mmu_idx);
}
/* Translate a S1 pagetable walk through S2 if needed. */

3
target/arm/tcg/cpregs-at.c
View File

@@ -37,8 +37,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
/*
* ATS operations only do S1 or S1+S2 translations, so we never
* have to deal with the ARMCacheAttrs format for S2 only.
* (Note that res fields are only valid on ptw success.)
*/
assert(!res.cacheattrs.is_s2_format);
assert(ret || !res.cacheattrs.is_s2_format);
if (ret) {
/*