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rust: pl011: use the bits macro

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This avoids the repeated ".0" when using the Interrupt struct.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
2025-06-03 17:45:05 +02:00
parent 648fe157d3
commit 9c8ff2a1ed
5 changed files with 49 additions and 44 deletions
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1
rust/Cargo.lock generated
View File

@@ -73,6 +73,7 @@ version = "0.1.0"
dependencies = [
"bilge",
"bilge-impl",
"bits",
"qemu_api",
"qemu_api_macros",
]

1
rust/hw/char/pl011/Cargo.toml
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@@ -18,6 +18,7 @@ crate-type = ["staticlib"]
[dependencies]
bilge = { version = "0.2.0" }
bilge-impl = { version = "0.2.0" }
bits = { path = "../../../bits" }
qemu_api = { path = "../../../qemu-api" }
qemu_api_macros = { path = "../../../qemu-api-macros" }

1
rust/hw/char/pl011/meson.build
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@@ -6,6 +6,7 @@ _libpl011_rs = static_library(
dependencies: [
bilge_rs,
bilge_impl_rs,
bits_rs,
qemu_api,
qemu_api_macros,
],

51
rust/hw/char/pl011/src/device.rs
View File

@@ -85,8 +85,8 @@ pub struct PL011Registers {
#[doc(alias = "cr")]
pub control: registers::Control,
pub dmacr: u32,
pub int_enabled: u32,
pub int_level: u32,
pub int_enabled: Interrupt,
pub int_level: Interrupt,
pub read_fifo: Fifo,
pub ilpr: u32,
pub ibrd: u32,
@@ -199,9 +199,9 @@ pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) {
LCR_H => u32::from(self.line_control),
CR => u32::from(self.control),
FLS => self.ifl,
IMSC => self.int_enabled,
RIS => self.int_level,
MIS => self.int_level & self.int_enabled,
IMSC => u32::from(self.int_enabled),
RIS => u32::from(self.int_level),
MIS => u32::from(self.int_level & self.int_enabled),
ICR => {
// "The UARTICR Register is the interrupt clear register and is write-only"
// Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR
@@ -263,13 +263,13 @@ pub(self) fn write(
self.set_read_trigger();
}
IMSC => {
self.int_enabled = value;
self.int_enabled = Interrupt::from(value);
return true;
}
RIS => {}
MIS => {}
ICR => {
self.int_level &= !value;
self.int_level &= !Interrupt::from(value);
return true;
}
DMACR => {
@@ -295,7 +295,7 @@ fn read_data_register(&mut self, update: &mut bool) -> u32 {
self.flags.set_receive_fifo_empty(true);
}
if self.read_count + 1 == self.read_trigger {
self.int_level &= !Interrupt::RX.0;
self.int_level &= !Interrupt::RX;
}
self.receive_status_error_clear.set_from_data(c);
*update = true;
@@ -305,7 +305,7 @@ fn read_data_register(&mut self, update: &mut bool) -> u32 {
fn write_data_register(&mut self, value: u32) -> bool {
// interrupts always checked
let _ = self.loopback_tx(value.into());
self.int_level |= Interrupt::TX.0;
self.int_level |= Interrupt::TX;
true
}
@@ -361,19 +361,19 @@ fn loopback_mdmctrl(&mut self) -> bool {
// Change interrupts based on updated FR
let mut il = self.int_level;
il &= !Interrupt::MS.0;
il &= !Interrupt::MS;
if self.flags.data_set_ready() {
il |= Interrupt::DSR.0;
il |= Interrupt::DSR;
}
if self.flags.data_carrier_detect() {
il |= Interrupt::DCD.0;
il |= Interrupt::DCD;
}
if self.flags.clear_to_send() {
il |= Interrupt::CTS.0;
il |= Interrupt::CTS;
}
if self.flags.ring_indicator() {
il |= Interrupt::RI.0;
il |= Interrupt::RI;
}
self.int_level = il;
true
@@ -391,8 +391,8 @@ pub fn reset(&mut self) {
self.line_control.reset();
self.receive_status_error_clear.reset();
self.dmacr = 0;
self.int_enabled = 0;
self.int_level = 0;
self.int_enabled = 0.into();
self.int_level = 0.into();
self.ilpr = 0;
self.ibrd = 0;
self.fbrd = 0;
@@ -451,7 +451,7 @@ pub fn fifo_rx_put(&mut self, value: registers::Data) -> bool {
}
if self.read_count == self.read_trigger {
self.int_level |= Interrupt::RX.0;
self.int_level |= Interrupt::RX;
return true;
}
false
@@ -632,7 +632,7 @@ fn update(&self) {
let regs = self.regs.borrow();
let flags = regs.int_level & regs.int_enabled;
for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
irq.set(flags & i != 0);
irq.set(flags.any_set(i));
}
}
@@ -642,14 +642,13 @@ pub fn post_load(&self, _version_id: u32) -> Result<(), ()> {
}
/// Which bits in the interrupt status matter for each outbound IRQ line ?
const IRQMASK: [u32; 6] = [
/* combined IRQ */
Interrupt::E.0 | Interrupt::MS.0 | Interrupt::RT.0 | Interrupt::TX.0 | Interrupt::RX.0,
Interrupt::RX.0,
Interrupt::TX.0,
Interrupt::RT.0,
Interrupt::MS.0,
Interrupt::E.0,
const IRQMASK: [Interrupt; 6] = [
Interrupt::all(),
Interrupt::RX,
Interrupt::TX,
Interrupt::RT,
Interrupt::MS,
Interrupt::E,
];
/// # Safety

39
rust/hw/char/pl011/src/registers.rs
View File

@@ -9,7 +9,8 @@
// https://developer.arm.com/documentation/ddi0183/latest/
use bilge::prelude::*;
use qemu_api::impl_vmstate_bitsized;
use bits::bits;
use qemu_api::{impl_vmstate_bitsized, impl_vmstate_forward};
/// Offset of each register from the base memory address of the device.
#[doc(alias = "offset")]
@@ -326,22 +327,24 @@ fn default() -> Self {
}
}
/// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
pub struct Interrupt(pub u32);
bits! {
/// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
#[derive(Default)]
pub struct Interrupt(u32) {
OE = 1 << 10,
BE = 1 << 9,
PE = 1 << 8,
FE = 1 << 7,
RT = 1 << 6,
TX = 1 << 5,
RX = 1 << 4,
DSR = 1 << 3,
DCD = 1 << 2,
CTS = 1 << 1,
RI = 1 << 0,
impl Interrupt {
pub const OE: Self = Self(1 << 10);
pub const BE: Self = Self(1 << 9);
pub const PE: Self = Self(1 << 8);
pub const FE: Self = Self(1 << 7);
pub const RT: Self = Self(1 << 6);
pub const TX: Self = Self(1 << 5);
pub const RX: Self = Self(1 << 4);
pub const DSR: Self = Self(1 << 3);
pub const DCD: Self = Self(1 << 2);
pub const CTS: Self = Self(1 << 1);
pub const RI: Self = Self(1 << 0);
pub const E: Self = Self(Self::OE.0 | Self::BE.0 | Self::PE.0 | Self::FE.0);
pub const MS: Self = Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0 | Self::CTS.0);
E = bits!(Self as u32: OE | BE | PE | FE),
MS = bits!(Self as u32: RI | DSR | DCD | CTS),
}
}
impl_vmstate_forward!(Interrupt);