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*: Remove arm host support

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Remove tcg/arm.
Remove instances of __arm__, except from tests and imported headers.
Remove arm from supported_cpus.
Remove linux-user/include/host/arm.
Remove common-user/host/arm.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-12-18 13:28:29 +11:00
parent 212d309af1
commit 581b722144
17 changed files with 5 additions and 3924 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@@ -4057,12 +4057,6 @@ S: Maintained
L: qemu-arm@nongnu.org
F: tcg/aarch64/
ARM TCG target
M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained
L: qemu-arm@nongnu.org
F: tcg/arm/
i386 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained

108
common-user/host/arm/safe-syscall.inc.S
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@@ -1,108 +0,0 @@
/*
* safe-syscall.inc.S : host-specific assembly fragment
* to handle signals occurring at the same time as system calls.
* This is intended to be included by common-user/safe-syscall.S
*
* Written by Richard Henderson <rth@twiddle.net>
* Copyright (C) 2016 Red Hat, Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
.global safe_syscall_base
.global safe_syscall_start
.global safe_syscall_end
.type safe_syscall_base, %function
.cfi_sections .debug_frame
.text
.syntax unified
.arm
.align 2
/* This is the entry point for making a system call. The calling
* convention here is that of a C varargs function with the
* first argument an 'int *' to the signal_pending flag, the
* second one the system call number (as a 'long'), and all further
* arguments being syscall arguments (also 'long').
*/
safe_syscall_base:
.fnstart
.cfi_startproc
mov r12, sp /* save entry stack */
push { r4, r5, r6, r7, r8, lr }
.save { r4, r5, r6, r7, r8, lr }
.cfi_adjust_cfa_offset 24
.cfi_rel_offset r4, 0
.cfi_rel_offset r5, 4
.cfi_rel_offset r6, 8
.cfi_rel_offset r7, 12
.cfi_rel_offset r8, 16
.cfi_rel_offset lr, 20
/* The syscall calling convention isn't the same as the C one:
* we enter with r0 == &signal_pending
* r1 == syscall number
* r2, r3, [sp+0] ... [sp+12] == syscall arguments
* and return the result in r0
* and the syscall instruction needs
* r7 == syscall number
* r0 ... r6 == syscall arguments
* and returns the result in r0
* Shuffle everything around appropriately.
* Note the 16 bytes that we pushed to save registers.
*/
mov r8, r0 /* copy signal_pending */
mov r7, r1 /* syscall number */
mov r0, r2 /* syscall args */
mov r1, r3
ldm r12, { r2, r3, r4, r5, r6 }
/* This next sequence of code works in conjunction with the
* rewind_if_safe_syscall_function(). If a signal is taken
* and the interrupted PC is anywhere between 'safe_syscall_start'
* and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'.
* The code sequence must therefore be able to cope with this, and
* the syscall instruction must be the final one in the sequence.
*/
safe_syscall_start:
/* if signal_pending is non-zero, don't do the call */
ldr r12, [r8] /* signal_pending */
tst r12, r12
bne 2f
swi 0
safe_syscall_end:
/* code path for having successfully executed the syscall */
#if defined(__linux__)
/* Linux kernel returns (small) negative errno. */
cmp r0, #-4096
neghi r0, r0
bhi 1f
#elif defined(__FreeBSD__)
/* FreeBSD kernel returns positive errno and C bit set. */
bcs 1f
#else
#error "unsupported os"
#endif
pop { r4, r5, r6, r7, r8, pc }
/* code path when we didn't execute the syscall */
2: mov r0, #QEMU_ERESTARTSYS
/* code path setting errno */
1: pop { r4, r5, r6, r7, r8, lr }
.cfi_adjust_cfa_offset -24
.cfi_restore r4
.cfi_restore r5
.cfi_restore r6
.cfi_restore r7
.cfi_restore r8
.cfi_restore lr
b safe_syscall_set_errno_tail
.fnend
.cfi_endproc
.size safe_syscall_base, .-safe_syscall_base

7
configure vendored
View File

@@ -418,8 +418,6 @@ elif check_define __riscv ; then
else
cpu="riscv32"
fi
elif check_define __arm__ ; then
cpu="arm"
elif check_define __aarch64__ ; then
cpu="aarch64"
elif check_define __loongarch64 ; then
@@ -451,11 +449,6 @@ case "$cpu" in
linux_arch=arm64
;;
armv*b|armv*l|arm)
cpu=arm
host_arch=arm
;;
i386|i486|i586|i686)
cpu="i386"
host_arch=i386

3
disas/disas-host.c
View File

@@ -74,9 +74,6 @@ static void initialize_debug_host(CPUDebug *s)
#elif defined(__sparc__)
s->info.print_insn = print_insn_sparc;
s->info.mach = bfd_mach_sparc_v9b;
#elif defined(__arm__)
/* TCG only generates code for arm mode. */
s->info.cap_arch = CS_ARCH_ARM;
#elif defined(__MIPSEB__)
s->info.print_insn = print_insn_big_mips;
#elif defined(__MIPSEL__)

2
hw/virtio/virtio-mem.c
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@@ -60,7 +60,7 @@ static uint32_t virtio_mem_default_thp_size(void)
{
uint32_t default_thp_size = VIRTIO_MEM_MIN_BLOCK_SIZE;
#if defined(__x86_64__) || defined(__arm__) || defined(__powerpc64__)
#if defined(__x86_64__) || defined(__powerpc64__)
default_thp_size = 2 * MiB;
#elif defined(__aarch64__)
if (qemu_real_host_page_size() == 4 * KiB) {

2
include/qemu/osdep.h
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@@ -566,7 +566,7 @@ int madvise(char *, size_t, int);
#endif
#if defined(__linux__) && \
(defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) \
(defined(__x86_64__) || defined(__aarch64__) \
|| defined(__powerpc64__) || defined(__riscv))
/* Use 2 MiB alignment so transparent hugepages can be used by KVM.
Valgrind does not support alignments larger than 1 MiB,

43
linux-user/include/host/arm/host-signal.h
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@@ -1,43 +0,0 @@
/*
* host-signal.h: signal info dependent on the host architecture
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2021 Linaro Limited
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef ARM_HOST_SIGNAL_H
#define ARM_HOST_SIGNAL_H
/* The third argument to a SA_SIGINFO handler is ucontext_t. */
typedef ucontext_t host_sigcontext;
static inline uintptr_t host_signal_pc(host_sigcontext *uc)
{
return uc->uc_mcontext.arm_pc;
}
static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
{
uc->uc_mcontext.arm_pc = pc;
}
static inline void *host_signal_mask(host_sigcontext *uc)
{
return &uc->uc_sigmask;
}
static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
{
/*
* In the FSR, bit 11 is WnR, assuming a v6 or
* later processor. On v5 we will always report
* this as a read, which will fail later.
*/
uint32_t fsr = uc->uc_mcontext.error_code;
return extract32(fsr, 11, 1);
}
#endif

2
linux-user/mmap.c
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@@ -1296,7 +1296,7 @@ static inline abi_ulong target_shmlba(CPUArchState *cpu_env)
}
#endif
#if defined(__arm__) || defined(__mips__) || defined(__sparc__)
#if defined(__mips__) || defined(__sparc__)
#define HOST_FORCE_SHMLBA 1
#else
#define HOST_FORCE_SHMLBA 0

7
meson.build
View File

@@ -51,7 +51,7 @@ qapi_trace_events = []
bsd_oses = ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly', 'darwin']
supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux', 'emscripten']
supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64',
'arm', 'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64']
'aarch64', 'loongarch64', 'mips64', 'sparc64', 'wasm64']
cpu = host_machine.cpu_family()
@@ -304,9 +304,6 @@ if cpu == 'x86'
xen_targets = ['i386-softmmu']
elif cpu == 'x86_64'
xen_targets = ['i386-softmmu', 'x86_64-softmmu']
elif cpu == 'arm'
# i386 emulator provides xenpv machine type for multiple architectures
xen_targets = ['i386-softmmu']
elif cpu == 'aarch64'
# i386 emulator provides xenpv machine type for multiple architectures
xen_targets = ['i386-softmmu', 'x86_64-softmmu', 'aarch64-softmmu']
@@ -3156,7 +3153,7 @@ endif
config_host_data.set('CONFIG_AVX2_OPT', have_avx2)
config_host_data.set('CONFIG_AVX512BW_OPT', have_avx512bw)
# For both AArch64 and AArch32, detect if builtins are available.
# For AArch64, detect if builtins are available.
config_host_data.set('CONFIG_ARM_AES_BUILTIN', cc.compiles('''
#include <arm_neon.h>
#ifndef __ARM_FEATURE_AES

47
tcg/arm/tcg-target-con-set.h
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@@ -1,47 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define Arm target-specific constraint sets.
* Copyright (c) 2021 Linaro
*/
/*
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I2(r, rIN)
C_O0_I2(q, q)
C_O0_I2(w, r)
C_O0_I3(q, q, q)
C_O0_I3(Q, p, q)
C_O0_I4(r, r, rI, rI)
C_O0_I4(Q, p, q, q)
C_O1_I1(r, q)
C_O1_I1(r, r)
C_O1_I1(w, r)
C_O1_I1(w, w)
C_O1_I1(w, wr)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, q, q)
C_O1_I2(r, r, r)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rI, r)
C_O1_I2(r, rI, rIK)
C_O1_I2(r, rI, rIN)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, 0, w)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wO)
C_O1_I2(w, w, wV)
C_O1_I2(w, w, wZ)
C_O1_I3(w, w, w, w)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(e, p, q)
C_O2_I2(e, p, q, q)
C_O2_I2(r, r, r, r)

26
tcg/arm/tcg-target-con-str.h
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@@ -1,26 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define Arm target-specific operand constraints.
* Copyright (c) 2021 Linaro
*/
/*
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
REGS('r', ALL_GENERAL_REGS)
REGS('q', ALL_QLDST_REGS)
REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */
REGS('w', ALL_VECTOR_REGS)
/*
* Define constraint letters for constants:
* CONST(letter, TCG_CT_CONST_* bit set)
*/
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
CONST('O', TCG_CT_CONST_ORRI)
CONST('V', TCG_CT_CONST_ANDI)
CONST('Z', TCG_CT_CONST_ZERO)

73
tcg/arm/tcg-target-has.h
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@@ -1,73 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define target-specific opcode support
* Copyright (c) 2008 Fabrice Bellard
* Copyright (c) 2008 Andrzej Zaborowski
*/
#ifndef TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_H
extern int arm_arch;
#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
#ifdef __ARM_ARCH_EXT_IDIV__
#define use_idiv_instructions 1
#else
extern bool use_idiv_instructions;
#endif
#ifdef __ARM_NEON__
#define use_neon_instructions 1
#else
extern bool use_neon_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1
#define TCG_TARGET_HAS_v64 use_neon_instructions
#define TCG_TARGET_HAS_v128 use_neon_instructions
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 1
#define TCG_TARGET_HAS_nand_vec 0
#define TCG_TARGET_HAS_nor_vec 0
#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_HAS_tst_vec 1
static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (use_armv7_instructions) {
return true; /* SBFX or UBFX */
}
switch (len) {
case 8: /* SXTB or UXTB */
case 16: /* SXTH or UXTH */
return (ofs % 8) == 0;
}
return false;
}
#define TCG_TARGET_extract_valid tcg_target_extract_valid
#define TCG_TARGET_sextract_valid tcg_target_extract_valid
#define TCG_TARGET_deposit_valid(type, ofs, len) use_armv7_instructions
#endif

13
tcg/arm/tcg-target-mo.h
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@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define target-specific memory model
* Copyright (c) 2008 Fabrice Bellard
* Copyright (c) 2008 Andrzej Zaborowski
*/
#ifndef TCG_TARGET_MO_H
#define TCG_TARGET_MO_H
#define TCG_TARGET_DEFAULT_MO 0
#endif

16
tcg/arm/tcg-target-opc.h.inc
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@@ -1,16 +0,0 @@
/*
* Copyright (c) 2019 Linaro
*
* This work is licensed under the terms of the GNU GPL, version 2 or
* (at your option) any later version.
*
* See the COPYING file in the top-level directory for details.
*
* Target-specific opcodes for host vector expansion. These will be
* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
* consider these to be UNSPEC with names.
*/
DEF(arm_sli_vec, 1, 2, 1, TCG_OPF_VECTOR)
DEF(arm_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR)
DEF(arm_ushl_vec, 1, 2, 0, TCG_OPF_VECTOR)

12
tcg/arm/tcg-target-reg-bits.h
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@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define target-specific register size
* Copyright (c) 2023 Linaro
*/
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS 32
#endif

3489
tcg/arm/tcg-target.c.inc
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File diff suppressed because it is too large Load Diff

73
tcg/arm/tcg-target.h
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@@ -1,73 +0,0 @@
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
* Copyright (c) 2008 Andrzej Zaborowski
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef ARM_TCG_TARGET_H
#define ARM_TCG_TARGET_H
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
TCG_REG_R12,
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_PC,
TCG_REG_Q0,
TCG_REG_Q1,
TCG_REG_Q2,
TCG_REG_Q3,
TCG_REG_Q4,
TCG_REG_Q5,
TCG_REG_Q6,
TCG_REG_Q7,
TCG_REG_Q8,
TCG_REG_Q9,
TCG_REG_Q10,
TCG_REG_Q11,
TCG_REG_Q12,
TCG_REG_Q13,
TCG_REG_Q14,
TCG_REG_Q15,
TCG_AREG0 = TCG_REG_R6,
TCG_REG_CALL_STACK = TCG_REG_R13,
} TCGReg;
#define TCG_TARGET_NB_REGS 32
#endif