f7a46c64c8
All these registers are already provided by via gdbstub parsed XML and handler by the gdb_get_register() helper in the monitor/hmp.c file. Remove as now unreachable code. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260219191955.83815-20-philmd@linaro.org>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/*
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* QEMU monitor for m68k
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or
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* later. See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "monitor/hmp.h"
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#include "monitor/hmp-target.h"
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#include "monitor/monitor.h"
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env1 = mon_get_cpu_env(mon);
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if (!env1) {
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monitor_printf(mon, "No CPU available\n");
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return;
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}
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dump_mmu(env1);
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}
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static const MonitorDef monitor_defs[] = {
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{ "ssp", offsetof(CPUM68KState, sp[0]), NULL, MD_I32 },
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{ "usp", offsetof(CPUM68KState, sp[1]), NULL, MD_I32 },
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{ "isp", offsetof(CPUM68KState, sp[2]), NULL, MD_I32 },
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{ "sfc", offsetof(CPUM68KState, sfc), NULL, MD_I32 },
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{ "dfc", offsetof(CPUM68KState, dfc), NULL, MD_I32 },
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{ "urp", offsetof(CPUM68KState, mmu.urp), NULL, MD_I32 },
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{ "srp", offsetof(CPUM68KState, mmu.srp), NULL, MD_I32 },
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{ "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]), NULL, MD_I32 },
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{ "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]), NULL, MD_I32 },
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{ "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]), NULL, MD_I32 },
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{ "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]), NULL, MD_I32 },
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{ "mmusr", offsetof(CPUM68KState, mmu.mmusr), NULL, MD_I32 },
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{ NULL },
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};
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const MonitorDef *target_monitor_defs(void)
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{
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return monitor_defs;
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}
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