Paolo Bonzini b3126dc77d target/i386: add more easy cases to gen_eflags_adcox ...

prepare_update_cf() sometimes results in CC_OP_ADCX, so this
improves a bit the handling of BT+RCL and the like.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2026-06-17 15:15:43 +02:00

..

alpha

fpu: Use {get,set}_flush_inputs_to_zero everywhere

2026-05-21 19:18:56 -07:00

arm

target/arm: Enable FEAT_F8F16MM for -cpu max

2026-06-10 16:54:40 +01:00

avr

target: Rename get_phys_page_debug to get_phys_addr_debug

2026-05-12 22:35:54 +02:00

hexagon

fpu: Use {get,set}_float_rounding_mode everywhere

2026-05-21 19:18:56 -07:00

hppa

target/hppa: Inline UNALIGN() macro

2026-05-27 12:27:21 +02:00

i386

target/i386: add more easy cases to gen_eflags_adcox

2026-06-17 15:15:43 +02:00

loongarch

target/loongarch: Add new structure CPUSysState

2026-06-09 08:37:18 -04:00

m68k

fpu: Use get_default_nan_mode everywhere

2026-05-21 19:18:56 -07:00

microblaze

target/microblaze: Convert to translate_for_debug

2026-05-29 13:18:38 +02:00

mips

linux-user/mips: save/restore FCSR across signal delivery

2026-05-29 23:40:53 +02:00

or1k

target: Rename get_phys_page_debug to get_phys_addr_debug

2026-05-12 22:35:54 +02:00

ppc

Merge tag 'pull-ppc-for-11.1-0523-20260523' of https://gitlab.com/harshpb/qemu into staging

2026-05-25 13:57:50 -04:00

riscv

target/riscv: add thead-c908 cpu support

2026-06-16 20:01:11 +10:00

rx

target: Rename get_phys_page_debug to get_phys_addr_debug

2026-05-12 22:35:54 +02:00

s390x

target/s390x: Make container ids in SysIB_15x 1-based

2026-06-05 12:30:33 +02:00

sh4

target/sh4: decode_gusa: recognize add#imm with prior mov Rm, Rn

2026-06-10 18:42:59 +02:00

sparc

target/sparc: Use cpu_translate_for_debug()

2026-05-12 22:35:54 +02:00

tricore

target: Rename get_phys_page_debug to get_phys_addr_debug

2026-05-12 22:35:54 +02:00

xtensa

target/xtensa: add cpu_set_fcr/fsr helpers to sync fp_status

2026-06-12 17:47:27 +02:00

Kconfig

target/or1k: Rename from openrisc

2026-02-09 20:51:52 +01:00

meson.build

target/or1k: Rename from openrisc

2026-02-09 20:51:52 +01:00