Files
qemu/tcg/riscv64/tcg-target-reg-bits.h
Richard Henderson 264ae24c36 meson: Drop host_arch rename for riscv64
This requires renaming several directories:
tcg/riscv, linux-user/include/host/riscv, and
common-user/host/riscv.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-01-17 10:46:07 +11:00

20 lines
408 B
C

/* SPDX-License-Identifier: MIT */
/*
* Define target-specific register size
* Copyright (c) 2018 SiFive, Inc
*/
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
/*
* We don't support oversize guests.
* Since we will only build tcg once, this in turn requires a 64-bit host.
*/
#if __riscv_xlen != 64
#error "unsupported code generation mode"
#endif
#define TCG_TARGET_REG_BITS 64
#endif