264ae24c36
This requires renaming several directories: tcg/riscv, linux-user/include/host/riscv, and common-user/host/riscv. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific opcode support
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* Copyright (c) 2018 SiFive, Inc
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*/
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#ifndef TCG_TARGET_HAS_H
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#define TCG_TARGET_HAS_H
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#include "host/cpuinfo.h"
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/* optional instructions */
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_tst 0
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/* vector instructions */
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#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_andc_vec 0
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#define TCG_TARGET_HAS_orc_vec 0
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#define TCG_TARGET_HAS_nand_vec 0
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#define TCG_TARGET_HAS_nor_vec 0
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#define TCG_TARGET_HAS_eqv_vec 0
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 0
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#define TCG_TARGET_HAS_roti_vec 1
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#define TCG_TARGET_HAS_rots_vec 1
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#define TCG_TARGET_HAS_rotv_vec 1
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 0
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#define TCG_TARGET_HAS_cmpsel_vec 1
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#define TCG_TARGET_HAS_tst_vec 0
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static inline bool
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tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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/* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
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return ofs || (cpuinfo & CPUINFO_ZBA);
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}
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switch (len) {
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case 1:
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return (cpuinfo & CPUINFO_ZBS) && ofs != 0;
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case 16:
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return (cpuinfo & CPUINFO_ZBB) && ofs == 0;
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}
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return false;
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}
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#define TCG_TARGET_extract_valid tcg_target_extract_valid
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static inline bool
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tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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return true;
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}
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return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
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}
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#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
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#define TCG_TARGET_deposit_valid(type, ofs, len) 0
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#endif
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