qemu/target at 05caa0624256da44974cd68e8f55dbbde3dfede7 - qemu

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Richard Henderson ded1db48c9 target/i386: Fix tss access size in switch_tss_ra

The two limit_max variables represent size - 1, just like the
encoding in the GDT, thus the 'old' access was off by one.
Access the minimal size of the new tss: the complete tss contains
the iopb, which may be a larger block than the access api expects,
and irrelevant because the iopb is not accessed during the
switch itself.

Fixes: 8b13106508 ("target/i386/tcg: use X86Access for TSS access")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2511
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240819074052.207783-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

2024-08-21 09:11:26 +10:00

alpha

target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation

2024-07-11 11:41:34 +01:00

arm

target/arm: Fix usage of MMU indexes when EL3 is AArch32

2024-08-13 11:44:53 +01:00

avr

target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation

2024-07-11 11:41:34 +01:00

cris

target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation