b3d4fc22f6
The tests do not test all of the FlexCAN emulator functionality. Signed-off-by: Matyáš Bobek <matyas.bobek@gmail.com> Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz> Tested-by: Pavel Pisa <pisa@fel.cvut.cz> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Pavel Pisa <pisa@fel.cvut.cz> Message-id: 3d47746ef30f29c58fec10267bdce7dac2c756a7.1782140438.git.matyas.bobek@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
422 lines
14 KiB
C
422 lines
14 KiB
C
/*
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* QTests for FlexCAN CAN controller device model
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*
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* Copyright (c) 2025 Matyas Bobek <matyas.bobek@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "hw/net/flexcan.h"
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#include "hw/net/can/flexcan_regs.h"
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#define FSL_IMX6_CAN2_ADDR 0x02094000
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#define FSL_IMX6_CAN2_SIZE 0x4000
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#define FSL_IMX6_CAN1_ADDR 0x02090000
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#define FSL_IMX6_CAN1_SIZE 0x4000
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#define FC_QEMU_ARGS "-nographic -M sabrelite " \
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"-object can-bus,id=qcan0 " \
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"-machine canbus0=qcan0 -machine canbus1=qcan0"
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/* used for masking out unused/reserved bits */
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#define FC_MB_CNT_USED_MASK (~0xF080FFFFu)
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#define FCREG(BASE_ADDR, REG) ((BASE_ADDR) + offsetof(FlexcanRegs, REG))
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#define FCMB(BASE_ADDR, MB_IDX, WORD_IDX) (FCREG(BASE_ADDR, mbs) + \
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0x10 * (MB_IDX) + 4 * (WORD_IDX))
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typedef struct FcTestFrame {
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uint32_t id;
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uint32_t data[2];
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uint8_t len;
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bool ide;
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bool rtr;
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/* rx only */
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bool expect_overrun;
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} FcTestFrame;
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static const FcTestFrame fc_test_frame_1 = {
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.id = 0x5AF,
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.len = 8,
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.data = {
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0x01020304,
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0x0A0B0C0D
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},
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.ide = false
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};
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static const FcTestFrame fc_test_frame_1_ide = {
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.id = 0x105AF5AF,
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.len = 8,
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.data = {
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0x01020304,
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0x0A0B0C0D
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},
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.ide = true
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};
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static void fc_reset(hwaddr ba, uint32_t mcr_flags)
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{
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/* disable */
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writel(FCREG(ba, mcr), 0xD890000F);
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/* enable in freeze mode */
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writel(FCREG(ba, mcr), 0x5980000F);
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/* soft reset */
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writel(FCREG(ba, mcr), 0x5980000F | FLEXCAN_MCR_SOFTRST);
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g_assert_cmpuint(readl(FCREG(ba, mcr)), ==, 0x5980000F);
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g_assert_cmpuint(readl(FCREG(ba, ctrl)), ==, 0);
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g_assert_cmpuint(readl(FCREG(ba, ctrl2)), ==, 0);
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writel(FCREG(ba, mcr), (0x5980000F & ~FLEXCAN_MCR_HALT) | mcr_flags);
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writel(FCREG(ba, ctrl2), FLEXCAN_CTRL2_RRS);
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/* initialize all mailboxes as rx inactive */
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for (int i = 0; i < FLEXCAN_MAILBOX_COUNT; i++) {
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writel(FCMB(ba, i, 0), FLEXCAN_MB_CODE_RX_INACTIVE);
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writel(FCMB(ba, i, 1), 0);
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writel(FCMB(ba, i, 2), 0);
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writel(FCMB(ba, i, 3), 0);
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}
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}
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static uint64_t fc_get_irqs(hwaddr ba)
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{
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return (uint64_t)readl(FCREG(ba, iflag1)) |
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((uint64_t)readl(FCREG(ba, iflag2)) << 32);
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}
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static void fc_clear_irq(hwaddr ba, int idx)
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{
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if (idx >= 32) {
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writel(FCREG(ba, iflag2), (uint32_t)1 << (idx - 32));
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} else {
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writel(FCREG(ba, iflag1), (uint32_t)1 << idx);
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}
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g_assert_cmpuint(fc_get_irqs(ba) & ((uint64_t)1 << idx), ==, 0);
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}
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static void fc_setup_rx_mb(hwaddr ba, int mbidx)
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{
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writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_RX_EMPTY);
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writel(FCMB(ba, mbidx, 1), 0);
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/* the data value should be ignored for RX mb */
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writel(FCMB(ba, mbidx, 2), 0);
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writel(FCMB(ba, mbidx, 3), 0);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)), ==, FLEXCAN_MB_CODE_RX_EMPTY);
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}
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static void fc_tx(hwaddr ba, int mbidx, const FcTestFrame *frame)
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{
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g_assert_cmpuint(frame->len, <=, 8);
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writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_TX_INACTIVE);
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uint32_t id = frame->ide ? frame->id : frame->id << 18;
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writel(FCMB(ba, mbidx, 1), id);
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writel(FCMB(ba, mbidx, 2), frame->data[0]);
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writel(FCMB(ba, mbidx, 3), frame->data[1]);
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uint32_t ctrl = FLEXCAN_MB_CODE_TX_DATA | FLEXCAN_MB_CNT_LENGTH(frame->len);
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if (frame->ide) {
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ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
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}
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if (frame->rtr) {
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ctrl |= FLEXCAN_MB_CNT_RTR;
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}
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writel(FCMB(ba, mbidx, 0), ctrl);
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/* check frame was transmitted */
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g_assert_cmpuint(fc_get_irqs(ba) & ((uint64_t)1 << mbidx),
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!=, 0);
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uint32_t xpectd_ctrl = (ctrl & ~FLEXCAN_MB_CODE_MASK) |
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FLEXCAN_MB_CODE_TX_INACTIVE;
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)) & FC_MB_CNT_USED_MASK, ==,
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xpectd_ctrl);
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/* other fields should stay unchanged */
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 1)), ==, id);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 2)), ==, frame->data[0]);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 3)), ==, frame->data[1]);
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}
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static void fc_rx_check(hwaddr ba, int mbidx, const FcTestFrame *frame)
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{
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uint32_t xpectd_ctrl = frame->expect_overrun ? FLEXCAN_MB_CODE_RX_OVERRUN
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: FLEXCAN_MB_CODE_RX_FULL;
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xpectd_ctrl |= FLEXCAN_MB_CNT_LENGTH(frame->len) | FLEXCAN_MB_CNT_SRR;
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if (frame->ide) {
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xpectd_ctrl |= FLEXCAN_MB_CNT_IDE;
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}
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if (frame->rtr) {
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xpectd_ctrl |= FLEXCAN_MB_CNT_RTR;
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}
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uint32_t xpectd_id = frame->ide ? frame->id : frame->id << 18;
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uint32_t ctrl = readl(FCMB(ba, mbidx, 0)) & FC_MB_CNT_USED_MASK;
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if ((ctrl & FLEXCAN_MB_CODE_MASK) == FLEXCAN_MB_CODE_RX_EMPTY) {
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fprintf(stderr, "expected frame (id=0x%X) not received\n", frame->id);
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}
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g_assert_cmpuint(ctrl, ==, xpectd_ctrl);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 1)), ==, xpectd_id);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 2)), ==, frame->data[0]);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 3)), ==, frame->data[1]);
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}
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static void fc_check_empty_multi(hwaddr ba, int idx_count, int mbidxs[])
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{
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for (int i = 0; i < FLEXCAN_MAILBOX_COUNT; i++) {
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bool check_empty = true;
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int ctrl = readl(FCMB(ba, i, 0));
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for (int j = 0; j < idx_count; j++) {
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if (i == mbidxs[j]) {
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check_empty = false;
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}
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}
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if (check_empty) {
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if (!(ctrl == FLEXCAN_MB_CODE_RX_EMPTY ||
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ctrl == FLEXCAN_MB_CODE_RX_INACTIVE)) {
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g_assert_cmpuint(ctrl, ==, FLEXCAN_MB_CODE_RX_INACTIVE);
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}
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g_assert_cmpuint(readl(FCMB(ba, i, 1)), ==, 0);
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g_assert_cmpuint(readl(FCMB(ba, i, 2)), ==, 0);
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g_assert_cmpuint(readl(FCMB(ba, i, 3)), ==, 0);
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} else {
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g_assert_cmpuint(
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ctrl & FLEXCAN_MB_CODE_MASK, !=,
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FLEXCAN_MB_CODE_RX_INACTIVE
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);
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}
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}
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}
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static void fc_check_empty(hwaddr ba, int mbidx)
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{
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fc_check_empty_multi(ba, 1, &mbidx);
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}
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static void flexcan_test_linux_probe_impl(hwaddr fba)
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{
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/* -- test a Linux driver-like probe sequence -- */
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/* disable */
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writel(FCREG(fba, mcr), 0xD890000F);
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xD890000F);
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g_assert_cmpuint(readl(FCREG(fba, ctrl)), ==, 0);
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/* set bit in reserved field we do not implement (CTRL_CLK_SRC) */
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writel(FCREG(fba, ctrl), 0x00002000);
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xD890000F);
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/* enable in freeze mode */
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writel(FCREG(fba, mcr), 0x5980000F);
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x5980000F);
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/* enable Rx-FIFO */
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writel(FCREG(fba, mcr), 0x7980000F);
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x7980000F);
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g_assert_cmpuint(readl(FCREG(fba, ecr)), ==, 0);
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/* disable */
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writel(FCREG(fba, mcr), 0xF890000F);
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xF890000F);
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}
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static void flexcan_test_freeze_disable_interaction_impl(hwaddr fba)
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{
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/* -- test normal <=> freeze <=> disable transitions -- */
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/* leave freeze in disabled, FRZ_ACK should stay cleared */
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writel(FCREG(fba, mcr), 0xF890000F); /* disable */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xF890000F);
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writel(FCREG(fba, mcr), 0xB890000F); /* by clearing FRZ */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xB890000F);
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writel(FCREG(fba, mcr), 0xF890000F); /* disable */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xF890000F);
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writel(FCREG(fba, mcr), 0xE890000F); /* by clearing HALT */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xE890000F);
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writel(FCREG(fba, mcr), 0xF890000F); /* disable */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xF890000F);
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writel(FCREG(fba, mcr), 0xA890000F); /* by clearing both */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0xA890000F);
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/* enter and leave freeze */
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writel(FCREG(fba, mcr), 0x7980000F); /* enable in freeze mode */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x7980000F);
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writel(FCREG(fba, mcr), 0x3980000F); /* leave by clearing FRZ */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x3080000F);
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writel(FCREG(fba, mcr), 0x7980000F); /* enable in freeze mode */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x7980000F);
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writel(FCREG(fba, mcr), 0x6980000F); /* leave by clearing HALT */
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g_assert_cmpuint(readl(FCREG(fba, mcr)), ==, 0x6080000F);
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}
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static void flexcan_test_mailbox_io_impl(hwaddr ba_tx, hwaddr ba_rx)
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{
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/* -- test correct handling of mailbox IO -- */
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const int test_1_mbidx = 0;
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fc_reset(ba_tx,
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FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT));
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fc_reset(ba_rx,
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FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT));
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fc_setup_rx_mb(ba_rx, test_1_mbidx);
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fc_tx(ba_tx, test_1_mbidx, &fc_test_frame_1_ide);
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g_assert_cmpuint(fc_get_irqs(ba_rx), ==, 1 << test_1_mbidx);
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fc_rx_check(ba_rx, test_1_mbidx, &fc_test_frame_1_ide);
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readl(FCREG(ba_rx, timer)); /* reset lock */
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writel(FCMB(ba_rx, test_1_mbidx, 0), 0);
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g_assert_cmpuint(readl(FCMB(ba_rx, test_1_mbidx, 0)), ==, 0);
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writel(FCMB(ba_rx, test_1_mbidx, 1), 0x99AABBCC);
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g_assert_cmpuint(readl(FCMB(ba_rx, test_1_mbidx, 1)), ==, 0x99AABBCC);
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}
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static void flexcan_test_dual_transmit_receive_impl(hwaddr ba_tx, hwaddr ba_rx)
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{
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/* -- test TX and RX between the two FlexCAN instances -- */
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const int test_1_mbidx = 50;
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const int test_rounds = 50;
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/* self-receive enabled on tx FC */
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fc_reset(ba_tx,
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FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT));
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fc_reset(ba_rx,
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FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT));
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/* tests self-receive on tx and reception on rx */
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fc_setup_rx_mb(ba_rx, test_1_mbidx);
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fc_check_empty(ba_rx, test_1_mbidx);
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fc_setup_rx_mb(ba_tx, test_1_mbidx + 1);
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fc_check_empty(ba_tx, test_1_mbidx + 1);
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g_assert_cmpuint(fc_get_irqs(ba_rx), ==, 0);
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g_assert_cmpuint(fc_get_irqs(ba_tx), ==, 0);
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fc_tx(ba_tx, test_1_mbidx, &fc_test_frame_1);
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fc_clear_irq(ba_tx, test_1_mbidx);
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fc_rx_check(ba_rx, test_1_mbidx, &fc_test_frame_1);
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fc_check_empty(ba_rx, test_1_mbidx);
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fc_rx_check(ba_tx, test_1_mbidx + 1, &fc_test_frame_1);
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int tx_non_empty_mbidxs[] = {test_1_mbidx, test_1_mbidx + 1};
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fc_check_empty_multi(ba_tx, 2, tx_non_empty_mbidxs);
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fc_clear_irq(ba_rx, test_1_mbidx);
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fc_clear_irq(ba_tx, test_1_mbidx + 1);
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readl(FCREG(ba_rx, timer)); /* reset lock */
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for (int ridx = 0; ridx < test_rounds; ridx++) {
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/* test extended IDs sent to all mailboxes */
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for (int i = 0; i < FLEXCAN_MAILBOX_COUNT; i++) {
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fc_setup_rx_mb(ba_rx, i);
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}
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fc_check_empty_multi(ba_rx, 0, NULL);
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g_assert_cmpuint(fc_get_irqs(ba_rx), ==, 0);
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g_assert_cmpuint(fc_get_irqs(ba_tx), ==, 0);
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for (int i = 0; i < FLEXCAN_MAILBOX_COUNT; i++) {
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fc_tx(ba_tx, i, &fc_test_frame_1_ide);
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}
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g_assert_cmpuint(fc_get_irqs(ba_rx), ==, UINT64_MAX);
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g_assert_cmpuint(fc_get_irqs(ba_tx), ==, UINT64_MAX);
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for (int i = 0; i < FLEXCAN_MAILBOX_COUNT; i++) {
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fc_rx_check(ba_rx, i, &fc_test_frame_1_ide);
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}
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/* reset interrupts */
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writel(FCREG(ba_rx, iflag1), UINT32_MAX);
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writel(FCREG(ba_rx, iflag2), UINT32_MAX);
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writel(FCREG(ba_tx, iflag1), UINT32_MAX);
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writel(FCREG(ba_tx, iflag2), UINT32_MAX);
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g_assert_cmpuint(fc_get_irqs(ba_rx), ==, 0);
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g_assert_cmpuint(fc_get_irqs(ba_tx), ==, 0);
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}
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}
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static void flexcan_test_tx_abort_impl(hwaddr ba)
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{
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/* -- test the TX abort feature -- */
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fc_reset(ba,
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FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT));
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for (int mbidx = 0; mbidx < FLEXCAN_MAILBOX_COUNT; mbidx++) {
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fc_tx(ba, mbidx, &fc_test_frame_1);
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writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_TX_ABORT);
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g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)), ==,
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FLEXCAN_MB_CODE_TX_INACTIVE);
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}
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}
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static void flexcan_test_freeze_disable_interaction(void)
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{
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qtest_start(FC_QEMU_ARGS);
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flexcan_test_freeze_disable_interaction_impl(FSL_IMX6_CAN1_ADDR);
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flexcan_test_freeze_disable_interaction_impl(FSL_IMX6_CAN2_ADDR);
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qtest_end();
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}
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static void flexcan_test_linux_probe(void)
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{
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qtest_start(FC_QEMU_ARGS);
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flexcan_test_linux_probe_impl(FSL_IMX6_CAN1_ADDR);
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flexcan_test_linux_probe_impl(FSL_IMX6_CAN2_ADDR);
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qtest_end();
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}
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static void flexcan_test_dual_transmit_receive(void)
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{
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qtest_start(FC_QEMU_ARGS);
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flexcan_test_dual_transmit_receive_impl(FSL_IMX6_CAN1_ADDR,
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FSL_IMX6_CAN2_ADDR);
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flexcan_test_dual_transmit_receive_impl(FSL_IMX6_CAN2_ADDR,
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FSL_IMX6_CAN1_ADDR);
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qtest_end();
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}
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static void flexcan_test_tx_abort(void)
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{
|
|
qtest_start(FC_QEMU_ARGS);
|
|
flexcan_test_tx_abort_impl(FSL_IMX6_CAN1_ADDR);
|
|
flexcan_test_tx_abort_impl(FSL_IMX6_CAN2_ADDR);
|
|
qtest_end();
|
|
}
|
|
|
|
static void flexcan_test_mailbox_io(void)
|
|
{
|
|
qtest_start(FC_QEMU_ARGS);
|
|
flexcan_test_mailbox_io_impl(FSL_IMX6_CAN1_ADDR, FSL_IMX6_CAN2_ADDR);
|
|
flexcan_test_mailbox_io_impl(FSL_IMX6_CAN2_ADDR, FSL_IMX6_CAN1_ADDR);
|
|
qtest_end();
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
g_test_init(&argc, &argv, NULL);
|
|
|
|
qtest_add_func("/net/flexcan/linux_probe", flexcan_test_linux_probe);
|
|
qtest_add_func("/net/flexcan/freeze_disable_interaction",
|
|
flexcan_test_freeze_disable_interaction);
|
|
qtest_add_func("/net/flexcan/dual_transmit_receive",
|
|
flexcan_test_dual_transmit_receive);
|
|
qtest_add_func("/net/flexcan/tx_abort",
|
|
flexcan_test_tx_abort);
|
|
qtest_add_func("/net/flexcan/mailbox_io", flexcan_test_mailbox_io);
|
|
|
|
return g_test_run();
|
|
}
|