Richard Henderson 79cabc6cb7 target/arm: Be more defensive for invalid tlbi_aa64_get_range ...

It's possible to program TCR_ELx with an invalid granule size,
which could match passing an invalid granule size to TLBI RVA,
which would then fall through to assert in arm_granule_bits.

Cc: qemu-stable@nongnu.org
Fixes: 3c003f7029 ("target/arm: Use ARMGranuleSize in ARMVAParameters")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-id: 20260710175818.528974-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2026-07-13 12:34:17 +01:00

..

hvf

Merge tag 'accel-20260706' of https://github.com/philmd/qemu into staging

2026-07-06 18:38:14 +02:00

tcg

target/arm: Be more defensive for invalid tlbi_aa64_get_range

2026-07-13 12:34:17 +01:00

whpx

accel: Remove AccelOpsClass::supports_guest_debug

2026-07-06 15:42:18 +02:00

arch_dump.c

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arm-powerctl.c

target/arm: teach arm_cpu_has_work about halting reasons

2026-06-10 16:54:40 +01:00

arm-powerctl.h

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arm-qmp-cmds.c

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common-semi-target.c

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cortex-regs.c

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cpregs-gcs.c

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cpregs-omap-stub.c

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cpregs-omap.c

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cpregs-pmu.c

target/arm: Connect internal interrupt sources up as GICv5 PPIs

2026-05-07 15:14:57 +01:00

cpregs.h

target/arm: Introduce FPMR

2026-05-26 11:41:00 +01:00

cpu32-stubs.c

target/arm: Rename Aarch64-specific methods

2026-05-15 08:52:42 +01:00

cpu64.c

target/arm: Define 'max' CPU type in cpu-max.c

2026-05-27 12:27:22 +02:00

cpu-features.h

target/arm: Implement SMOP4[AS] (4-way)

2026-07-06 11:32:01 +01:00

cpu-irq.c

target/arm: Restrict TCG specific headers

2026-06-18 14:27:15 +02:00

cpu-max.c

docs/system: declare support for FEAT_EVT2

2026-07-13 12:34:17 +01:00

cpu-param.h

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cpu-qom.h

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cpu-sysregs.h

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cpu-sysregs.h.inc

target/arm: Implement ID_AA64FPFR0

2026-05-26 11:41:00 +01:00

cpu.c

target/arm: Define fields for NSACR

2026-07-06 11:32:01 +01:00

cpu.h

target/arm: ensure we create the wxft_timer for all modes

2026-07-06 11:32:01 +01:00

debug_helper.c

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el2-stubs.c

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gdbstub64.c

linux-user: add MTE_STORE_ONLY to prctl

2026-06-10 16:54:03 +01:00

gdbstub.c

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gtimer.h

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helper-a64.h

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helper-fp8.h

target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD

2026-06-10 16:54:40 +01:00

helper-mve.h

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helper-sme.h

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helper-sve.h

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helper.c

target/arm: Define fields for NSACR

2026-07-06 11:32:01 +01:00

helper.h

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hvf_arm.h

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hyp_gdbstub.c

accel: Use GdbBreakpointType enum

2026-07-06 15:42:18 +02:00

internals.h

Merge tag 'accel-20260706' of https://github.com/philmd/qemu into staging

2026-07-06 18:38:14 +02:00

Kconfig

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kvm_arm.h

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kvm-consts.h

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kvm-stub.c

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kvm.c

cpu: Introduce cpu_single_stepping() helper

2026-07-06 15:42:18 +02:00

machine.c

target/arm: Better describe PMU depends on TCG or HVF

2026-06-18 14:27:13 +02:00

meson.build

target/arm: move kvm-stub to arm_stubs_ss

2026-05-28 18:43:56 +02:00

mmuidx-internal.h

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mmuidx.c

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mmuidx.h

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multiprocessing.h

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ptw.c

target/arm: Only evaluate SCR_EL3.PIEN if ARM_FEATURE_EL3 is present

2026-07-06 11:32:01 +01:00

syndrome.h

target/arm: Separate syndrome functions for A32 and A64

2026-07-06 11:32:01 +01:00

tcg-stubs.c

target/arm: Connect internal interrupt sources up as GICv5 PPIs

2026-05-07 15:14:57 +01:00

trace-events

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trace.h

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vector-type.h

target/arm: Split vector-type.h from cpu.h

2026-05-26 11:41:00 +01:00

vfp_fpscr.c

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whpx_arm.h

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