b7d2329469
The nest MMU is used for translations needed by I/O subsystems on Power10. The nest is the shared, on-chip infrastructure that connects CPU cores, memory controllers, and I/O. This patch sets up a basic skeleton with its xscom area, mapping both needed xscom regions. Support required for PowerVM bringup. Use Power9 property for device tree to allow OPAL to work with Power9 and Power10. Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260120150139.714805-1-calebs@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
/*
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* QEMU PowerPC nest MMU model
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*
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* Copyright (c) 2025, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_nmmu.h"
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#include "hw/ppc/fdt.h"
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#include <libfdt.h>
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#define NMMU_XLAT_CTL_PTCR 0xb
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static uint64_t pnv_nmmu_xscom_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvNMMU *nmmu = PNV_NMMU(opaque);
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int reg = addr >> 3;
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uint64_t val;
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if (reg == NMMU_XLAT_CTL_PTCR) {
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val = nmmu->ptcr;
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} else {
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val = 0xffffffffffffffffull;
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qemu_log_mask(LOG_UNIMP, "nMMU: xscom read at 0x%" PRIx32 "\n", reg);
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}
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return val;
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}
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static void pnv_nmmu_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvNMMU *nmmu = PNV_NMMU(opaque);
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int reg = addr >> 3;
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if (reg == NMMU_XLAT_CTL_PTCR) {
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nmmu->ptcr = val;
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} else {
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qemu_log_mask(LOG_UNIMP, "nMMU: xscom write at 0x%" PRIx32 "\n", reg);
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}
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}
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static const MemoryRegionOps pnv_nmmu_xscom_ops = {
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.read = pnv_nmmu_xscom_read,
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.write = pnv_nmmu_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_nmmu_realize(DeviceState *dev, Error **errp)
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{
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PnvNMMU *nmmu = PNV_NMMU(dev);
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assert(nmmu->chip);
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/* NMMU xscom region */
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pnv_xscom_region_init(&nmmu->xscom_regs, OBJECT(nmmu),
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&pnv_nmmu_xscom_ops, nmmu,
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"xscom-nmmu",
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PNV10_XSCOM_NMMU_SIZE);
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}
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static int pnv_nmmu_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int offset)
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{
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PnvNMMU *nmmu = PNV_NMMU(dev);
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char *name;
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int nmmu_offset;
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const char compat[] = "ibm,power9-nest-mmu";
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uint32_t nmmu_pcba = PNV10_XSCOM_NEST0_MMU_BASE + nmmu->nmmu_id * 0x1000000;
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uint32_t reg[2] = {
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cpu_to_be32(nmmu_pcba),
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cpu_to_be32(PNV10_XSCOM_NMMU_SIZE)
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};
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name = g_strdup_printf("nmmu@%x", nmmu_pcba);
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nmmu_offset = fdt_add_subnode(fdt, offset, name);
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_FDT(nmmu_offset);
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g_free(name);
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_FDT(fdt_setprop(fdt, nmmu_offset, "reg", reg, sizeof(reg)));
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_FDT(fdt_setprop(fdt, nmmu_offset, "compatible", compat, sizeof(compat)));
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return 0;
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}
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static const Property pnv_nmmu_properties[] = {
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DEFINE_PROP_UINT32("nmmu_id", PnvNMMU, nmmu_id, 0),
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DEFINE_PROP_LINK("chip", PnvNMMU, chip, TYPE_PNV_CHIP, PnvChip *),
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};
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static void pnv_nmmu_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass);
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xscomc->dt_xscom = pnv_nmmu_dt_xscom;
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dc->desc = "PowerNV nest MMU";
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dc->realize = pnv_nmmu_realize;
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device_class_set_props(dc, pnv_nmmu_properties);
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}
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static const TypeInfo pnv_nmmu_info = {
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.name = TYPE_PNV_NMMU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvNMMU),
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.class_init = pnv_nmmu_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PNV_XSCOM_INTERFACE },
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{ }
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}
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};
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static void pnv_nmmu_register_types(void)
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{
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type_register_static(&pnv_nmmu_info);
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}
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type_init(pnv_nmmu_register_types);
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