774e6f5c15
The bus-frequency property in the CPU FDT node was hardcoded to 0. This is incorrect - it should reflect the actual platform bus clock frequency, as firmware and RTOSes use it to derive peripheral clock rates. Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC global timer interval. With bus-frequency=0, the timer interval overflows to ~85 seconds, preventing any clock interrupts from firing. Fix by adding a bus_freq field to PPCE500MachineClass and using it in the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for existing machines, matching the existing clock_freq value. Signed-off-by: Vivien LEGER <vivien.leger@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20260411154535.1451361-1-vivien.leger@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
#ifndef PPCE500_H
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#define PPCE500_H
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#include "hw/core/boards.h"
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#include "hw/core/platform-bus.h"
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#include "qom/object.h"
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#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
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struct PPCE500MachineState {
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/*< private >*/
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MachineState parent_obj;
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/* points to instance of TYPE_PLATFORM_BUS_DEVICE if
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* board supports dynamic sysbus devices
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*/
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PlatformBusDevice *pbus_dev;
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};
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struct PPCE500MachineClass {
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/*< private >*/
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MachineClass parent_class;
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/* required -- must at least add toplevel board compatible */
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void (*fixup_devtree)(void *fdt);
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int pci_first_slot;
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int pci_nr_slots;
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int mpic_version;
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bool has_mpc8xxx_gpio;
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bool has_esdhc;
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hwaddr platform_bus_base;
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hwaddr platform_bus_size;
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int platform_bus_first_irq;
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int platform_bus_num_irqs;
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hwaddr ccsrbar_base;
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hwaddr pci_pio_base;
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hwaddr pci_mmio_base;
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hwaddr pci_mmio_bus_base;
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hwaddr spin_base;
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uint32_t clock_freq;
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uint32_t bus_freq;
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uint32_t tb_freq;
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};
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void ppce500_init(MachineState *machine);
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#define TYPE_PPCE500_MACHINE "ppce500-base-machine"
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OBJECT_DECLARE_TYPE(PPCE500MachineState, PPCE500MachineClass, PPCE500_MACHINE)
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#endif
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