Commit Graph

3799 Commits

Author SHA1 Message Date
Stefan Hajnoczi
b0df6e2f2c Merge tag 'pull-riscv-to-apply-20260616' of https://github.com/alistair23/qemu into staging
RISC-V PR for 11.1

* Disable svpbmt if satp_mode is less then sv39
* Fix PMP address alignment
* Mstatus write bug fixes
* Add 'cbo' insns to disassembler
* Do not hide Sstc CSRs from gdbstub
* Reject Svinval instructions in U-mode
* Save opcode before zicbo helpers
* Fault with reserved PTE.PBMT val
* Allow LOAD_ADDR_MIS promotion to AMO fault
* Make riscv cpu.h target independent
* Add PMA access fault
* Disable svnapot if satp_mode is less then sv39
* Fix disassembler inst_length calculation
* Add RISC-V big-endian target support
* Add the implied rules for G and B extensions
* Print privilege level and ELP in riscv_cpu_dump_state
* Improve alignment in riscv_cpu_dump_state
* Mask vxrm csrw write to the low 2 bits
* Reorder Smrnmi CPU fields above CPU reset line
* Supplement cpu topology arguments
* Don't insert DDT cache in Bare mode
* Fix 'iommu-map' FDT entry
* Fix mstatus.FS dirty tracking for FP exception-raising instructions
* Enable `mnret` disassembly
* Add support for K230 board
* FDT creation helpers

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# gpg: Signature made Tue 16 Jun 2026 06:04:49 EDT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20260616' of https://github.com/alistair23/qemu: (83 commits)
  hw/riscv: add create_fdt_socket_cpu_sifive()
  hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal()
  hw/riscv/spike.c: use create_fdt_socket_cpus()
  hw/riscv: add create_fdt_socket_cpus()
  hw/riscv: add fdt_create_cpu_socket_subnode() helper
  hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs
  hw/riscv: add create_fdt_clint() helper
  hw/riscv/spike.c: add intc_phandles array
  hw/riscv/sifive_u.c: add intc_phandles array
  hw/riscv: add create_fdt_socket_memory() helper
  hw/riscv/numa: make numa_enabled() public
  hw/riscv: add fdt-common helper
  hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc
  docs/system/riscv: add documentation for k230 machine
  tests/qtest: add test for K230 watchdog
  hw/watchdog: add k230 watchdog initial support
  hw/riscv: add k230 board initial support
  target/riscv: add thead-c908 cpu support
  disas/riscv: enable `mnret` disassembly
  target/riscv: rvv: Set mstatus.FS dirty when vector FP raises exceptions
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-16 10:41:47 -04:00
Chao Liu
b3fe55196f docs/system/riscv: add documentation for k230 machine
Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <81d2e2fa42ecabf638f841321cf36cee8f10af01.1781246408.git.chao.liu@processmission.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-06-16 20:01:11 +10:00
Djordje Todorovic
a8dc227c83 target/riscv: Expose and document the CPU 'big-endian' property
Now that the full big-endian data path is in place (runtime MSTATUS
bits, boot code, and page-table walks), expose the "big-endian"
property to users via DEFINE_PROP_BOOL and document it in
docs/system/target-riscv.rst.

Document that the property models fixed-endian hardware: it selects
harts whose MBE/SBE/UBE fields are fixed to 1, and it does not model
a mixed-endian implementation where software can toggle those bits at
runtime.

The property can be enabled from the command line, e.g.:

    -cpu <cpu>,big-endian=on

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20260527201348.29511-12-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-06-16 13:53:36 +10:00
Stefan Hajnoczi
608ad9307d Merge tag 'pbouvier/pr/tests-20260615' of https://gitlab.com/p-b-o/qemu into staging
Changes:
- [PATCH v2 0/5] tests: update ubuntu2204 to ubuntu2404 (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
  Link: https://lore.kernel.org/qemu-devel/20260610192222.2709135-1-pierrick.bouvier@oss.qualcomm.com

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# gpg: Signature made Mon 15 Jun 2026 13:50:44 EDT
# gpg:                using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197  3FDB B444 37D1 9C28 62DF

* tag 'pbouvier/pr/tests-20260615' of https://gitlab.com/p-b-o/qemu:
  tests: remove ubuntu2204 container
  ci: update to ubuntu2404
  docs: update mention to ubuntu2204
  tests: add ubuntu 2404
  net/af-xdp.c: maybe-uninitialized warning with gcov build on ubuntu2404

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-15 16:48:38 -04:00
Stefan Hajnoczi
dfd6387bf9 Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
pci, vhost, virtio, iommu: features, fixes, cleanups

intel_iommu:
    PASID support for passthrough
    some properties renamed
virtio-rtc:
    new device
acpi:
    watchdog (x86 q35)
    COM irqs are now shared
vhost-user:
    vhost-user passes GPA not HVA now
    vhost SHMEM_MAP/UNMAP support
vhost-vdpa:
    svq IN_ORDER support
amd_iommu:
    IOMMU XT interrupt support
    command buffer fixes
cxl:
    PPR support
    performant path for non-interleaved cases
vhost-scsi:
    build fix for older kernel headers
fixes, cleanups all over the place

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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# gpg: Signature made Mon 15 Jun 2026 15:57:49 EDT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (106 commits)
  hw/scsi/vhost-scsi: fix build with older kernel headers
  tests/qtest: add 8-byte MMIO access sweep for intel-iommu
  intel_iommu: fix guest-triggerable abort on oversized MMIO access
  hw/cxl: Add a performant (and correct) path for the non interleaved cases
  hw/cxl: Allow cxl_cfmws_find_device() to filter on whether interleaved paths are accepted
  hw/cxl/events: Fix handling of component ID in event records generation to not assume it is a string
  hw/cxl: Add fixes in Post Package Repair (PPR)
  hw/cxl: Fix handling of component ID to not assume it is a string
  vhost-user.rst: fix typo
  vhost-user-device: Add shared memory BAR
  qmp: add shmem feature map
  vhost_user.rst: Add GET_SHMEM_CONFIG message
  vhost_user: Add frontend get_shmem_config command
  vhost_user.rst: Add SHMEM_MAP/_UNMAP to spec
  vhost_user.rst: Align VhostUserMsg excerpt members
  vhost-user: Add VirtIO Shared Memory map request
  tests: acpi: x86/q35: update expected WDAT blob
  tests: acpi: x86/q35: add WDAT table test case
  tests: acpi: x86/q35: whitelist new WDAT table
  x86: q35: generate WDAT ACPI table
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-15 16:47:02 -04:00
Pierrick Bouvier
f011b0d5d1 docs: update mention to ubuntu2204
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260610192222.2709135-4-pierrick.bouvier@oss.qualcomm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
2026-06-15 10:50:03 -07:00
Stefan Hajnoczi
b21adc910a Merge tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
 * Emulate various FP8 related features: FEAT_F8F16MM, FEAT_F8F32MM,
   FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2, FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4,
   FEAT_FP8FMA, FEAT_SSVE_FP8FMA, FEAT_SME_LUTv2, FEAT_FP8, FEAT_LUT
 * Emulate MTE4 features: FEAT_MTE_CANONICAL_TAGS,
   FEAT_MTE_NO_ADDRESS_TAGS, FEAT_MTE_PERM,FEAT_MTE_STORE_ONLY,
   FEAT_MTE_TAGGED_FAR
 * target/arm: fix WFET typo in syndrome
 * target/arm: Preparatory patches for implementing WFE
 * hw/dma/pl080: Don't use hw_error() for unimplemented features
 * hw/intc/exynos4210_combiner: Avoid hw_error for guest errors
 * hw/usb/hcd-ohci: Clean up USBPacket before freeing ISO TD packet
 * hw/core/qdev-clock: Fix potential null pointer dereference

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# gpg: Signature made Wed 10 Jun 2026 11:58:17 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu: (71 commits)
  target/arm: Enable FEAT_F8F16MM for -cpu max
  target/arm: Implement FMMLA (FP8 to FP16) for SVE
  target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD
  target/arm: Enable FEAT_F8F32MM for -cpu max
  target/arm: Implement FMMLA (FP8 to FP32) for SVE
  target/arm: Implement FMMLA (FP8 to FP32) for AdvSIMD
  target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max
  target/arm: Implement FDOT (FP8 to FP16) for SVE
  target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD
  target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max
  target/arm: Implement FDOT (FP8 to FP32) for SVE
  target/arm: Implement FDOT (FP8 to FP32) for AdvSIMD
  target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max
  target/arm: Implement FMLALL{BB,BT,TB,TT} for SVE
  target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD
  target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE
  target/arm: Implement FMLALB, FMLALT for AdvSIMD
  target/arm: Enable FEAT_SME_LUTv2 for -cpu max
  target/arm: Implement LUTI4 (four registers, 8-bit)
  target/arm: Implement MOVT (vector to table)
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-11 13:22:33 -04:00
Richard Henderson
c45b02cb24 target/arm: Enable FEAT_F8F16MM for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
97f97d15c7 target/arm: Enable FEAT_F8F32MM for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
c67d5463da target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
908c7a23d5 target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
07e9ea8f1c target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
332ec0f79b target/arm: Enable FEAT_SME_LUTv2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
a918a18f0e target/arm: Enable FEAT_FP8 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Richard Henderson
215ad1fa32 target/arm: Enable FEAT_LUT for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:40 +01:00
Gabriel Brookman
f35b6418cc docs: add MTE4 features to docs
The implemented MTE4 features are now present in
docs/system/arm/emulation.rst

Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260529-feat-mte4-v7-13-ccbd3c14eb3c@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-06-10 16:54:25 +01:00
Denis V. Lunev
7e8cc6c886 qemu-img: add sub-command --remove-all to 'qemu-img bitmap'
From time to time it is needed to remove all bitmaps from the image.
Before this patch the process is not very convenient. One should
perform
    qemu-img info
and parse the output to obtain all names. After that one should
sequentially call
    qemu-img bitmap --remove
for each present bitmap.

The patch adds --remove-all sub-command to 'qemu-img bitmap'. The
new sub-command also composes with other bitmap actions in the same
invocation, so a common "wipe and recreate" workflow can be expressed
as
    qemu-img bitmap --remove-all --add NEW FILE
instead of enumerating existing bitmaps, removing them one by one,
and only then adding the fresh one.

Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Denis V. Lunev <den@openvz.org>
Message-ID: <20260520235952.500250-1-den@openvz.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2026-06-08 17:00:46 +02:00
Stefan Hajnoczi
29c042c6e9 lcitool: remove Cirrus CI support
Remove GitLab CI integration for Cirrus CI now that nothing uses it
anymore.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20260602162457.828969-3-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-03 12:45:38 -04:00
Alexandr Moshkov
480be4f43b vhost-user.rst: fix typo
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alexandr Moshkov <dtalexundeer@yandex-team.ru>
Reviewed-by: Raphael Norwitz <rnorwitz@nvidia.com>
Message-Id: <20260330095226.158386-2-dtalexundeer@yandex-team.ru>
2026-06-03 08:36:42 -04:00
Albert Esteve
060ed6a4bb vhost_user.rst: Add GET_SHMEM_CONFIG message
Add GET_SHMEM_CONFIG vhost-user frontend
message to the spec documentation.

Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Alyssa Ross <hi@alyssa.is>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260304165223.2166175-6-aesteve@redhat.com>
2026-06-03 08:36:42 -04:00
Albert Esteve
588acb45c2 vhost_user.rst: Add SHMEM_MAP/_UNMAP to spec
Add SHMEM_MAP/_UNMAP request to the vhost-user
spec documentation.

Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Alyssa Ross <hi@alyssa.is>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260304165223.2166175-4-aesteve@redhat.com>
2026-06-03 08:36:42 -04:00
Albert Esteve
8d0e94927a vhost_user.rst: Align VhostUserMsg excerpt members
Add missing members to the VhostUserMsg excerpt in
the vhost-user spec documentation.

Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260304165223.2166175-3-aesteve@redhat.com>
2026-06-03 08:36:42 -04:00
Jorge E. Moreira
08c2415217 vhost-user.rst: Explicitly allow front-end to write to kick FDs
Migration of back-end state happens while the device is suspended (i.e
all vrings are stopped). To resume normal operation on the destination,
the vrings need to be started again with a kick (either a write on the
FD or the VHOST_USER_VRING_KICK in-band message if negotiated). While
these notifications are typically sent by the driver, it has no reason
to send them in the destination if it already sent them in the source as
the driver is unaware that a migration took place. Therefore it should
be the responsibility of the vhost-user front-end to ensure these vrings
are started. This is particularly necessary for queues where data only
flows from device to driver, such as those used by the vsock and input
devices.

This behavior is already used by some qemu vhost-user front-ends (e.g
vhost-user-blk) and by front-ends implemented on other VMMs(e.g CrosVm).
Adding it to the vhost-user documentation makes it explicit that this
strategy is permitted and suggest it to vhost-user front-end authors.
Explicitly documenting it is necessary because vring kicks appear
designed to originate in the driver, so having some originate in the
front-end can be counterintuitive and cause developers to waste time
looking for other alternatives or face pushback during code review.

Signed-off-by: Jorge E. Moreira <jemoreira@google.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260411021205.3592118-1-jemoreira@google.com>
2026-06-03 08:36:12 -04:00
Vladimir Sementsov-Ogievskiy
be51b7177c vhost-user: add VHOST_USER_PROTOCOL_F_GPA_ADDRESSES
Unlike the kernel, vhost-user backend knows nothing about QEMU's
userspace addresses. We can pass GPA instead and nothing changes.
Generally, vhost-user servers need these addresses only to calculate
offsets inside memory regions. Still, some servers (QEMU's internal
is one example) may do checks for passed addresses to be "userspace
addresses", for example check for non-zero. That's why we need
additional negotiation for the feature.

The benefit: this opens the doors for further implementation of
local migration (live-update) with passing open vhost-related FDs
through UNIX domain socket. This way the connection with backend is
kept live and untouched.

Without this change, we would have to communicate with backend to
inform it about UVA address changes, but it's better to simply use
more stable GPA numbers, which don't change after migration.

Additionally, the current implementation exposes QEMU's process
address space by passing UVA, which breaks ASLR. New protocol
feature avoids that.

Note, that we do nothing with backend messages and replies.
Frontends have to work with backends userspace addresses anyway,
because they come from userfaultfd.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Based-on: <20260206095258.894504-1-vsementsov@yandex-team.ru>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260420202032.714884-11-vsementsov@yandex-team.ru>
2026-06-03 08:36:12 -04:00
Zhenzhong Duan
c068e00cff intel_iommu: Change 'flts' property naming to 'fsts'
Previous patch Removed 'x-' prefix from 'x-flts' property.
Opportunistically, this patch does s/flts/fsts for property name
in order to better align with newer spec since revision 3.4 which
changed terminology from "First-level" to "First-stage".

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260513064227.2304854-3-zhenzhong.duan@intel.com>
2026-06-03 08:36:11 -04:00
Zhenzhong Duan
08dc347e52 intel_iommu: Remove 'x-' prefix from 'x-scalable-mode' and 'x-flts' properties
We had 'x-scalable-mode' for more than 5 years and 'x-flts' for more than 1
year, it's fine to remove 'x-' now.

This is a prerequisite to enable intel_iommu's scalable mode and first stage
translation support in libvirt.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260513064227.2304854-2-zhenzhong.duan@intel.com>
2026-06-03 08:36:11 -04:00
Philippe Mathieu-Daudé
faf1bfdd63 docs/devel/tcg-ops: Fix reStructuredText format
In the standard reStructuredText inline markup, italic
text is surrounded by one asterisk.

Fix incomplete style from commits 5e97a28a8b ("tcg: convert
tcg/README to rst") and 76f4278029 ("tcg: Add add/sub with
carry opcodes and infrastructure").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260519210019.11665-1-philmd@linaro.org>
2026-05-29 13:03:39 -07:00
Stefan Hajnoczi
81cc5f39aa Merge tag 'pull-target-arm-20260529' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
 * target/arm: Implement FEAT_CMPBR emulation
 * target/arm: Implement FEAT_RNG_TRAP emulation
 * target/arm: Don't assert if 64-bit EL2 AT insn sees a Domain fault
 * target/arm: SME BFCVT, BFCVTN have "Alternate BFloat16 behaviors"
 * target/arm: Enable REVD for SVE2.1
 * zynq: Various minor bug fixes
 * hw/misc: Add dummy ZYNQ DDR controller
 * hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
 * hw/dma/omap_dma: Remove unused ifdeffed out code

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# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260529' of https://gitlab.com/pm215/qemu: (21 commits)
  hw/dma/omap_dma: Fix indentation after ifdef removal
  hw/dma/omap_dma: Fix coding style in omap_dma_transfer_setup()
  hw/dma/omap_dma: Remove unused ifdeffed out code
  target/arm: advertise FEAT_RNG_TRAP on cortex-max
  target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS
  target/arm: SME BFCVT, BFCVTN have "Alternate BFloat16 behaviors"
  target/arm: Don't assert if 64-bit EL2 AT insn sees a Domain fault
  target/arm: Enable FEAT_CMPBR for -cpu max
  target/arm: Implement CB (immediate)
  target/arm: Implement CB, CBB, CBH
  target/arm: Add feature predicate for FEAT_CMPBR
  hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation files
  hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
  hw/misc/zynq_slcr: Add logic for DCI configuration
  hw/misc: Add dummy ZYNQ DDR controller
  hw/dma/zynq-devcfg: Indicate power-up status of PL
  hw/dma/zynq-devcfg: Simulate dummy PL reset
  hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode
  hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
  hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-29 12:58:25 -04:00
Jason Wright
7e637052fa target/arm: advertise FEAT_RNG_TRAP on cortex-max
Set ID_AA64PFR1.RNDR_TRAP=1 on the max CPU model so guests and
firmware detect FEAT_RNG_TRAP, per the Arm Architecture Reference
Manual for A-profile architecture (DDI 0487), and document the feature
as emulated in docs/system/arm/emulation.rst.

Signed-off-by: Jason Wright <wrigjl@proton.me>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-29 09:44:03 +01:00
Philippe Mathieu-Daudé
510899e681 docs/devel/tcg-ops: List more vector opcodes
Few logical and arithmetic vector opcodes are missing, list them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20260504125032.35465-3-philmd@linaro.org>
2026-05-28 17:53:49 +02:00
Philippe Mathieu-Daudé
c2188eb551 docs/devel/tcg-ops: Stop listing dup2_vec()
dup2_vec() opcode was removed in commit 6e7b13936d
("tcg: Remove INDEX_op_dup2_vec").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260504125032.35465-2-philmd@linaro.org>
2026-05-28 17:53:49 +02:00
Richard Henderson
5e18eaab88 target/arm: Enable FEAT_CMPBR for -cpu max
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260518174750.660258-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-28 15:06:23 +01:00
Stefan Hajnoczi
3f89b5de5b Merge tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
 * hw/timer/mss_timer: Remove dead code in timer_write()
 * OMAP: Remove various pieces of dead code
 * target/arm: Set debug in attrs in translate_for_debug()
 * target/arm/ptw: Flip sense of get_phys_addr_* return values
 * tests/functional/aarch64: Bump up timeout on vbsa
 * target/arm: Fix minor FEAT_AFP corner case bugs
 * target/arm: Implement FEAT_FAMINMAX
 * target/arm: Implement FEAT_FPMR
 * target/arm: Some initial patches towards other FP8 features

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# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu: (54 commits)
  target/arm: Move vectors_overlap to vec_internal.h
  target/arm: Split vector-type.h from cpu.h
  target/arm: Implement FSCALE for SME
  target/arm: Implement FSCALE for AdvSIMD
  target/arm: Add isar_feature_aa64_f8cvt
  target/arm: Implement ID_AA64FPFR0
  target/arm: Enable FEAT_FPMR for -cpu max
  linux-user/aarch64: Implement FPMR signal frames
  target/arm: Dump FPMR when present
  tests/functional/aarch64/rme: update images to support FEAT_FP8
  target/arm: Trap direct acceses to FPMR
  target/arm: Add FPMR_EL to TBFLAGS
  target/arm: Clear FPMR on ResetSVEState
  target/arm: Enable EnFPM bits for FEAT_FPMR
  target/arm: Update SCTLR bits for FEAT_FPMR
  target/arm: Introduce FPMR
  target/arm: Update HCRX bits for Arm ARM M.a.a
  target/arm: Update SCR bits for Arm ARM M.a.a
  target/arm: Enable FEAT_FAMINMAX for -cpu max
  target/arm: Implement FEAT_FAMINMAX for SVE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-26 13:20:15 -04:00
Richard Henderson
2430d49a17 target/arm: Enable FEAT_FPMR for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-26 11:41:00 +01:00
Richard Henderson
697910f67f target/arm: Enable FEAT_FAMINMAX for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-05-26 11:41:00 +01:00
Jamin Lin
4ed26771eb docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
Update the Aspeed AST10x0 documentation to include the
AST1040 evaluation board and clarify the AST10x0 family
classification.

The documentation now describes:
- AST1030 and AST1040 as Bridge IC devices
- AST1060 as a Platform Root of Trust processor
- AST1040 Cortex-M4F CPU frequency running at 400 MHz

Also add the ast1040-evb machine entry to the supported
AST10x0 SoC based machine list.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
2026-05-26 07:13:49 +02:00
William de Abreu Pinho
dc238e34f2 hw/arm/aspeed: add anacapa-bmc machine
Add the Facebook Anacapa BMC machine.  The I2C topology is based on the
Linux kernel device tree [1].  Hardware strap register values are taken
from real hardware.

A functional test is included using the OpenBMC image built from [2],
similar to the tests for bletchley-bmc and catalina-bmc.

[1]: 76b4ec8efd/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
[2]: 8e22df918e

Signed-off-by: William de Abreu Pinho <williamdapinho@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260519-add-anacapa-machine-v3-2-56c23993a20a@gmail.com
[ clg: docs/system/arm/aspeed.rst : fixed 'Aspeed family boards' title change ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
2026-05-24 23:14:14 +02:00
Stefan Hajnoczi
cbf877d67a Merge tag 'pbouvier/pr/docs-20260522' of https://gitlab.com/p-b-o/qemu into staging
Changes:
- [PATCH] docs/code-provenance: Fix formatting of *-by tags (=?utf-8?q?J=2E_Neusch=C3=A4fer?= <j.neuschaefer@9elements.com>)
  Link: https://lore.kernel.org/qemu-devel/20260520-prov-v1-1-7a58af334b9c@9elements.com
- [PATCH] docs/devel/qom: Fix some editing errors (=?utf-8?q?J=2E_Neusch=C3=A4fer?= <j.neuschaefer@9elements.com>)
  Link: https://lore.kernel.org/qemu-devel/20260520-qom-v1-1-baad87fefe4f@9elements.com
- [PATCH] docs/devel: Fix typo (s/exist paths/exit paths/) (=?utf-8?q?J=2E_Neusch=C3=A4fer?= <j.neuschaefer@9elements.com>)
  Link: https://lore.kernel.org/qemu-devel/20260520-exist-v1-1-535f929a87ae@9elements.com

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# gpg: Signature made Fri 22 May 2026 14:52:54 EDT
# gpg:                using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197  3FDB B444 37D1 9C28 62DF

* tag 'pbouvier/pr/docs-20260522' of https://gitlab.com/p-b-o/qemu:
  docs/devel: Fix typo (s/exist paths/exit paths/)
  docs/devel/qom: Fix some editing errors
  docs/code-provenance: Fix formatting of *-by tags

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-24 07:45:19 -04:00
Stefan Hajnoczi
fcabc76ddf Merge tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu into staging
RISC-V PR for 11.1.

* Remove spike as default machine
* Deprecate the shakti_c machine
* Set MISA.[C|X] based on the selected extensions
* Update Maintainers for OpenSBI Firmware
* Update OpenSBI to v1.8.1
* Avoid RISCVCPU copy in PMU FDT setup
* A collection of specification compliance improvements
* Fix Svnapot 64KB pages
* Handle source overlap of vector widening reduction instructions
* Check interrupt in SiFive UART after txctrl register is written
* Fix medeleg[11] read-only zero bit for M-mode ECALL
* Fix tail handling for vmv.s.x and vfmv.s.f
* Update the local AIA interrupt mask
* Add KVM support for Zicbop and BFloat16 extensions
* Fix the IOMMU FSC SV32 capability check
* Avoid caching PCI device IDs in the IOMMU
* Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
* Remove the internal CPU riscv_cpu_* arrays
* Fix IOCOUNTINH.CY toggle detection
* Fix the read of pmpaddr(0-63) CSRs
* Make hpmcounterh return the upper 32-bits
* Minor fixes and enhancements of RISC-V AIA devices
* Re-process IOMMU command queue after clearing CMD_ILL

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# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu: (48 commits)
  hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL
  hw/intc: riscv_aplic: add trace events of APLIC read/write function
  hw/intc: riscv_imsic: Add reset API to IMSIC
  hw/intc: riscv_aplic: Add reset API to APLIC
  hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
  target/riscv: Make hpmcounterh return the upper 32-bits
  hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping
  target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs
  hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection
  target/riscv/cpu: remove riscv_cpu_* arrays
  target/riscv/tcg: use isa_edata_arr[] to create user props
  target/riscv: do not set defaults in cpu prop callback
  target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
  target/riscv/tcg: use isa_edata_arr[] to enable max exts
  target/riscv/kvm: use isa_edata_arr[] for unavailable props
  target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
  target/riscv: remove riscv_cpu_named_features[]
  target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
  target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
  target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-24 07:44:52 -04:00
Stefan Hajnoczi
4c4b309510 Merge tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu into staging
Misc patches for iotests, qom, crypt & io

 * Fix client side anoymous TLS credentials
 * Fix return value semantics for qio_channel_flush
 * Add ID validation of internal QOM constructor
 * Fix ability to create internal QOM objects
   without a parent
 * Merge user creatable object constructor into
   main QOM file
 * Print reason for skipping I/O tests
 * Remove redundant meson suits for I/O tests
 * Add optional suites for many block drivers I/O tests
 * Run I/O tests for 10 block drivers in GitLab CI
 * Fix sudo check for LUKS I/O test
 * Mark I/O test 151, 181, 185, 308 as flaky

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# gpg: Signature made Thu 21 May 2026 09:48:57 EDT
# gpg:                using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full]
# gpg:                 aka "Daniel P. Berrange <berrange@redhat.com>" [full]
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E  8E3F BE86 EBB4 1510 4FDF

* tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu: (29 commits)
  qom: drop user_creatable_add_type method
  qom: allow object_new_with_prop* to trigger module loading
  qom: fix ability to create objects without a parent
  qom: add object_new_with_props_from_qdict
  qom: move object_set_prop_keyval into object.c
  qom: have object_set_props_keyval return bool
  qom: shorten name of object_set_properties_from_keyval
  qom: make errp last param in methods taking va_list
  qom: validate ID format when creating objects
  hw/vfio-user: use a valid object ID for iothread
  qom: add trace events for object/property lifecycle
  gitlab: remove I/O tests from build-tcg-disabled job
  gitlab: add jobs for thorough block tests
  iotests: mark 151, 181, 185 & 308 as flaky tests
  iotests: fix check for sudo access in LUKS I/O test
  iotests: validate dmsetup result in test 128
  iotests: use 'driver' as collective term for either format or protocol
  iotests: add nbd and luks to the I/O test suites
  docs/devel/testing: expand documentation for 'make check-block'
  iotests: add a meson suite / make target per block I/O tests format
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-05-24 07:44:37 -04:00
J. Neuschäfer
6a570c504f docs/devel: Fix typo (s/exist paths/exit paths/)
In the discussion of control flow through a function, "exit paths" were meant.

Signed-off-by: J. Neuschäfer <j.neuschaefer@9elements.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260520-exist-v1-1-535f929a87ae@9elements.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
2026-05-22 11:52:32 -07:00
J. Neuschäfer
c033b47f13 docs/devel/qom: Fix some editing errors
"devices have an two additional [...]" -> "devices have two additional",
and also a case of "were" vs. "where".

Signed-off-by: J. Neuschäfer <j.neuschaefer@9elements.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260520-qom-v1-1-baad87fefe4f@9elements.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
2026-05-22 11:52:32 -07:00
J. Neuschäfer
2f127af408 docs/code-provenance: Fix formatting of *-by tags
Applying both ``code`` and **bold** formatting doesn't have the intended
outcome, instead Sphinx emits the backticks into the HTML.

Use only **bold** formatting to fix the HTML output.

Signed-off-by: J. Neuschäfer <j.neuschaefer@9elements.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260520-prov-v1-1-7a58af334b9c@9elements.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
2026-05-22 11:52:32 -07:00
Alistair Francis
0e466ba898 target/riscv: Deprecate the shakti_c machine
The RISC-V shakti_c machine hasn't had meaningful contributions since 2021
and is currently unmaintained. The machine is scheduled to be removed as it
appears to have no users.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260430052218.771358-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-05-22 09:45:46 +10:00
Alistair Francis
44adb5fcc2 target/riscv: Remove spike as default machine
In QEMU 10.0 we deprecated the default spike machine, let's finally
remove spike as the default and require users to specify the machine.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260430052218.771358-2-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-05-22 09:45:46 +10:00
Daniel P. Berrangé
a9c326e080 iotests: use 'driver' as collective term for either format or protocol
The I/O tests integration previously exclusively tested block formats
and now also covers the NBD protocol. Replace references to 'format'
with 'driver', as a generic term to collectively apply to either a
format or protocol.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2026-05-21 12:39:54 +01:00
Daniel P. Berrangé
922891df9a iotests: add nbd and luks to the I/O test suites
This introduces new suites for running I/O tests on NBD and LUKS
drivers, giving new make targets

 * make check-block-luks
 * make check-block-nbd

as well as adding their tests to 'make check-block SPEED=thorough'

Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2026-05-21 12:39:54 +01:00
Daniel P. Berrangé
d63c082a43 docs/devel/testing: expand documentation for 'make check-block'
Explain in greater detail what 'check-block' will run for each format,
and also document the new format specific targets.

Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2026-05-21 12:39:54 +01:00
Philippe Mathieu-Daudé
630decdfcc buildsys: Remove MIPS KVM
We removed support for MIPS host. The KVM MIPS code
is now unreachable, remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260511135312.38705-5-philmd@linaro.org>
2026-05-21 08:20:58 +02:00
Philippe Mathieu-Daudé
bfa0801e91 buildsys: Remove support for MIPS hosts
MIPS host support is deprecated since commit 269ffaabc8
("buildsys: Remove support for 32-bit MIPS hosts"). Time
to remove.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260511135312.38705-3-philmd@linaro.org>
2026-05-21 08:20:58 +02:00