From fe1958cdb697435966ef66eb3507366edbb2e50e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 15 Feb 2026 02:51:34 +0100 Subject: [PATCH] target/sparc: Expose gdbstub registers to sparc32 targets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import gdb-xml/sparc32-{cpu,fpu,cp0}.xml from mainstream binutils, tag 'binutils-2_46', found in the gdb/features/sparc/folder [*]. Register them by setting the CPUClass::gdb_core_xml_file field and calling gdb_register_coprocessor() in sparc_cpu_register_gdb_regs(). [*] https://sourceware.org/git/?p=binutils-gdb.git;a=tree;f=gdb/features/sparc;hb=refs/tags/binutils-2_46 Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20260219191955.83815-16-philmd@linaro.org> --- configs/targets/sparc-linux-user.mak | 1 + configs/targets/sparc-softmmu.mak | 1 + gdb-xml/sparc32-cp0.xml | 18 ++++++++++++ gdb-xml/sparc32-cpu.xml | 42 ++++++++++++++++++++++++++++ gdb-xml/sparc32-fpu.xml | 42 ++++++++++++++++++++++++++++ target/sparc/cpu.c | 2 +- target/sparc/gdbstub.c | 13 +++++---- 7 files changed, 113 insertions(+), 6 deletions(-) create mode 100644 gdb-xml/sparc32-cp0.xml create mode 100644 gdb-xml/sparc32-cpu.xml create mode 100644 gdb-xml/sparc32-fpu.xml diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak index d3f0716ca2..01446e2878 100644 --- a/configs/targets/sparc-linux-user.mak +++ b/configs/targets/sparc-linux-user.mak @@ -2,5 +2,6 @@ TARGET_ARCH=sparc TARGET_SYSTBL_ABI=common,32 TARGET_SYSTBL=syscall.tbl TARGET_BIG_ENDIAN=y +TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml TARGET_LONG_BITS=32 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index c4c38946d5..ed846735f4 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,5 +1,6 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y +TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml TARGET_LONG_BITS=32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/gdb-xml/sparc32-cp0.xml b/gdb-xml/sparc32-cp0.xml new file mode 100644 index 0000000000..eacd89cf3b --- /dev/null +++ b/gdb-xml/sparc32-cp0.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + diff --git a/gdb-xml/sparc32-cpu.xml b/gdb-xml/sparc32-cpu.xml new file mode 100644 index 0000000000..242295c886 --- /dev/null +++ b/gdb-xml/sparc32-cpu.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/sparc32-fpu.xml b/gdb-xml/sparc32-fpu.xml new file mode 100644 index 0000000000..38217ca7a9 --- /dev/null +++ b/gdb-xml/sparc32-fpu.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d82f858efb..1493336e7a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1095,7 +1095,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data) #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_core_xml_file = "sparc64-cpu.xml"; #else - cc->gdb_num_core_regs = 72; + cc->gdb_core_xml_file = "sparc32-cpu.xml"; #endif cc->tcg_ops = &sparc_tcg_ops; } diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index b5b1494950..ed52e521dc 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -43,7 +43,6 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } -__attribute__((unused)) static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CPUSPARCState *env = cpu_env(cs); @@ -79,7 +78,6 @@ static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } -__attribute__((unused)) static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { CPUSPARCState *env = cpu_env(cs); @@ -154,7 +152,6 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #endif } -__attribute__((unused)) static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUSPARCState *env = cpu_env(cs); @@ -197,7 +194,6 @@ static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #endif } -__attribute__((unused)) static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUSPARCState *env = cpu_env(cs); @@ -271,7 +267,14 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) void sparc_cpu_register_gdb_regs(CPUState *cs) { #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - /* Not yet supported */ + gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register, + sparc_fpu_gdb_write_register, + gdb_find_static_feature("sparc32-fpu.xml"), + 0); + gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, + sparc_cp0_gdb_write_register, + gdb_find_static_feature("sparc32-cp0.xml"), + 0); #else gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register, sparc_fpu_gdb_write_register,