From a0b0643890becbbd3c2bfbf004a929438cfd58d6 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 3 Jul 2026 15:05:30 -0300 Subject: [PATCH] hw/riscv/riscv_hart.c isolate tcg only bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit riscv_cpu_register_csr_qtest_callback(), vcsr_call() and csr_qtest_callback() are all TCG only and are not available in --disable-tcg builds. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20260703180538.3346781-19-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv_hart.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index d1c7188369..747754be61 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -61,7 +61,7 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) { RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); @@ -151,8 +151,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp) s->harts = g_new0(RISCVCPU, s->num_harts); -#ifndef CONFIG_USER_ONLY - riscv_cpu_register_csr_qtest_callback(); +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + if (qtest_enabled()) { + riscv_cpu_register_csr_qtest_callback(); + } #endif for (n = 0; n < s->num_harts; n++) {