From 797fffedac9355495c010a12d4766517db2aa911 Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Thu, 29 Jan 2026 13:32:04 +0000 Subject: [PATCH] hw/arm/smmu-common: Make iommu ops part of SMMUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make iommu ops part of SMMUState and set to the current default smmu_ops. No functional change intended. This will allow SMMUv3 accel implementation to set a different iommu ops later. Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 7 +++++-- include/hw/arm/smmu-common.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 1492d7dd95..58c4452b1f 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -959,6 +959,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) "smmu-secure-memory-view"); } + if (!s->iommu_ops) { + s->iommu_ops = &smmu_ops; + } /* * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra * root complexes to be associated with SMMU. @@ -978,9 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) } if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, s->iommu_ops, s); } return; } diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index f5060cf36f..7b975abc25 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -166,6 +166,7 @@ struct SMMUState { AddressSpace memory_as; MemoryRegion *secure_memory; AddressSpace secure_memory_as; + const PCIIOMMUOps *iommu_ops; }; struct SMMUBaseClass {