From 412c48d054b484a0f88d858dc554c24e07e94358 Mon Sep 17 00:00:00 2001 From: Alexey Gerasimenko Date: Fri, 13 Mar 2026 16:47:16 +0000 Subject: [PATCH] q35: Fix incorrect values for PCIEXBAR masks There are two small issues in PCIEXBAR address mask handling: - wrong bit positions for address mask bits (see PCIEXBAR description in Q35 datasheet) - incorrect usage of 64ADR_MASK Due to this, attempting to write a valid PCIEXBAR address may cause it to shift to another address, causing memory layout corruption where emulated MMIO regions may overlap real (passed through) MMIO ranges. Fix this by providing correct values. Fixes: df2d8b3ed4 ("q35: Introduce q35 pc based chipset emulator") Signed-off-by: Alexey Gerasimenko Signed-off-by: Thierry Escande Reviewed-by: Michael S. Tsirkin Message-Id: <20260313164649.794591-4-thierry.escande@vates.tech> Signed-off-by: Michael S. Tsirkin --- hw/pci-host/q35.c | 6 +++--- include/hw/pci-host/q35.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e85e4227b3..7368e3c598 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -306,12 +306,12 @@ static void mch_update_pciexbar(MCHPCIState *mch) break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: length = 128 * 1024 * 1024; - addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | - MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: length = 64 * 1024 * 1024; - addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK | + MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index ddafc3f2e3..f31a71010b 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -100,8 +100,8 @@ struct Q35PCIHost { #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) -#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) -#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) +#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 27)) +#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 26)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))